Merge commit 'v2.6.33-rc2' into for-2.6.33

3 files changed, 6 insertions, 30 deletions

diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S
index c657de59abca..74a7f4130b4c 100644
--- a/arch/powerpc/lib/copy_32.S
+++ b/arch/powerpc/lib/copy_32.S
@@ -98,20 +98,7 @@ _GLOBAL(cacheable_memzero)
         bdnz    4b
 3:      mtctr   r9
         li      r7,4
-#if !defined(CONFIG_8xx)
 10:     dcbz    r7,r6
-#else
-10:     stw     r4, 4(r6)
-        stw     r4, 8(r6)
-        stw     r4, 12(r6)
-        stw     r4, 16(r6)
-#if CACHE_LINE_SIZE >= 32
-        stw     r4, 20(r6)
-        stw     r4, 24(r6)
-        stw     r4, 28(r6)
-        stw     r4, 32(r6)
-#endif /* CACHE_LINE_SIZE */
-#endif
         addi    r6,r6,CACHELINE_BYTES
         bdnz    10b
         clrlwi  r5,r8,32-LG_CACHELINE_BYTES
@@ -200,9 +187,7 @@ _GLOBAL(cacheable_memcpy)
         mtctr   r0
         beq     63f
 53:
-#if !defined(CONFIG_8xx)
         dcbz    r11,r6
-#endif
         COPY_16_BYTES
 #if L1_CACHE_BYTES >= 32
         COPY_16_BYTES
@@ -356,14 +341,6 @@ _GLOBAL(__copy_tofrom_user)
         li      r11,4
         beq     63f
 
-#ifdef CONFIG_8xx
-        /* Don't use prefetch on 8xx */
-        mtctr   r0
-        li      r0,0
-53:     COPY_16_BYTES_WITHEX(0)
-        bdnz    53b
-
-#else /* not CONFIG_8xx */
         /* Here we decide how far ahead to prefetch the source */
         li      r3,4
         cmpwi   r0,1
@@ -416,7 +393,6 @@ _GLOBAL(__copy_tofrom_user)
         li      r3,4
         li      r7,0
         bne     114b
-#endif /* CONFIG_8xx */
 
 63:     srwi.   r0,r5,2
         mtctr   r0
diff --git a/arch/powerpc/lib/copypage_64.S b/arch/powerpc/lib/copypage_64.S
index 75f3267fdc30..e68beac0a171 100644
--- a/arch/powerpc/lib/copypage_64.S
+++ b/arch/powerpc/lib/copypage_64.S
@@ -26,11 +26,11 @@ BEGIN_FTR_SECTION
         srd     r8,r5,r11
 
         mtctr   r8
-setup:
+.Lsetup:
         dcbt    r9,r4
         dcbz    r9,r3
         add     r9,r9,r12
-        bdnz    setup
+        bdnz    .Lsetup
 END_FTR_SECTION_IFSET(CPU_FTR_CP_USE_DCBTZ)
         addi    r3,r3,-8
         srdi    r8,r5,7         /* page is copied in 128 byte strides */
diff --git a/arch/powerpc/lib/locks.c b/arch/powerpc/lib/locks.c
index 79d0fa3a470d..58e14fba11b1 100644
--- a/arch/powerpc/lib/locks.c
+++ b/arch/powerpc/lib/locks.c
@@ -25,7 +25,7 @@
 #include <asm/smp.h>
 #include <asm/firmware.h>
 
-void __spin_yield(raw_spinlock_t *lock)
+void __spin_yield(arch_spinlock_t *lock)
 {
         unsigned int lock_value, holder_cpu, yield_count;
 
@@ -55,7 +55,7 @@ void __spin_yield(raw_spinlock_t *lock)
  * This turns out to be the same for read and write locks, since
  * we only know the holder if it is write-locked.
  */
-void __rw_yield(raw_rwlock_t *rw)
+void __rw_yield(arch_rwlock_t *rw)
 {
         int lock_value;
         unsigned int holder_cpu, yield_count;
@@ -82,7 +82,7 @@ void __rw_yield(raw_rwlock_t *rw)
 }
 #endif
 
-void __raw_spin_unlock_wait(raw_spinlock_t *lock)
+void arch_spin_unlock_wait(arch_spinlock_t *lock)
 {
         while (lock->slock) {
                 HMT_low();
@@ -92,4 +92,4 @@ void __raw_spin_unlock_wait(raw_spinlock_t *lock)
         HMT_medium();
 }
 
-EXPORT_SYMBOL(__raw_spin_unlock_wait);
+EXPORT_SYMBOL(arch_spin_unlock_wait);