KVM: PPC: Book3S HV: Support POWER6 compatibility mode on POWER7

This enables us to use the Processor Compatibility Register (PCR) on
POWER7 to put the processor into architecture 2.05 compatibility mode
when running a guest.  In this mode the new instructions and registers
that were introduced on POWER7 are disabled in user mode.  This
includes all the VSX facilities plus several other instructions such
as ldbrx, stdbrx, popcntw, popcntd, etc.

To select this mode, we have a new register accessible through the
set/get_one_reg interface, called KVM_REG_PPC_ARCH_COMPAT.  Setting
this to zero gives the full set of capabilities of the processor.
Setting it to one of the "logical" PVR values defined in PAPR puts
the vcpu into the compatibility mode for the corresponding
architecture level.  The supported values are:

0x0f000002	Architecture 2.05 (POWER6)
0x0f000003	Architecture 2.06 (POWER7)
0x0f100003	Architecture 2.06+ (POWER7+)

Since the PCR is per-core, the architecture compatibility level and
the corresponding PCR value are stored in the struct kvmppc_vcore, and
are therefore shared between all vcpus in a virtual core.

Signed-off-by: Paul Mackerras <paulus@samba.org>
[agraf: squash in fix to add missing break statements and documentation]
Signed-off-by: Alexander Graf <agraf@suse.de>

2 files changed, 49 insertions, 2 deletions

diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 2a0e38feec1d..e42fb5448608 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -166,6 +166,35 @@ void kvmppc_set_pvr(struct kvm_vcpu *vcpu, u32 pvr)
         vcpu->arch.pvr = pvr;
 }
 
+int kvmppc_set_arch_compat(struct kvm_vcpu *vcpu, u32 arch_compat)
+{
+        unsigned long pcr = 0;
+        struct kvmppc_vcore *vc = vcpu->arch.vcore;
+
+        if (arch_compat) {
+                if (!cpu_has_feature(CPU_FTR_ARCH_206))
+                        return -EINVAL; /* 970 has no compat mode support */
+
+                switch (arch_compat) {
+                case PVR_ARCH_205:
+                        pcr = PCR_ARCH_205;
+                        break;
+                case PVR_ARCH_206:
+                case PVR_ARCH_206p:
+                        break;
+                default:
+                        return -EINVAL;
+                }
+        }
+
+        spin_lock(&vc->lock);
+        vc->arch_compat = arch_compat;
+        vc->pcr = pcr;
+        spin_unlock(&vc->lock);
+
+        return 0;
+}
+
 void kvmppc_dump_regs(struct kvm_vcpu *vcpu)
 {
         int r;
@@ -826,6 +855,9 @@ int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id, union kvmppc_one_reg *val)
         case KVM_REG_PPC_PPR:
                 *val = get_reg_val(id, vcpu->arch.ppr);
                 break;
+        case KVM_REG_PPC_ARCH_COMPAT:
+                *val = get_reg_val(id, vcpu->arch.vcore->arch_compat);
+                break;
         default:
                 r = -EINVAL;
                 break;
@@ -936,6 +968,9 @@ int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id, union kvmppc_one_reg *val)
         case KVM_REG_PPC_PPR:
                 vcpu->arch.ppr = set_reg_val(id, *val);
                 break;
+        case KVM_REG_PPC_ARCH_COMPAT:
+                r = kvmppc_set_arch_compat(vcpu, set_reg_val(id, *val));
+                break;
         default:
                 r = -EINVAL;
                 break;
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index a81979becf41..cd39632a646e 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -499,7 +499,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
         addis   r8,r8,0x100     /* if so, increment upper 40 bits */
         mtspr   SPRN_TBU40,r8
 
-37:     li      r0,1
+        /* Load guest PCR value to select appropriate compat mode */
+37:     ld      r7, VCORE_PCR(r5)
+        cmpdi   r7, 0
+        beq     38f
+        mtspr   SPRN_PCR, r7
+38:
+        li      r0,1
         stb     r0,VCORE_IN_GUEST(r5)   /* signal secondaries to continue */
         b       10f
 
@@ -1094,8 +1100,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
         addis   r8,r8,0x100             /* if so, increment upper 40 bits */
         mtspr   SPRN_TBU40,r8
 
+        /* Reset PCR */
+17:     ld      r0, VCORE_PCR(r5)
+        cmpdi   r0, 0
+        beq     18f
+        li      r0, 0
+        mtspr   SPRN_PCR, r0
+18:
         /* Signal secondary CPUs to continue */
-17:     li      r0,0
         stb     r0,VCORE_IN_GUEST(r5)
         lis     r8,0x7fff               /* MAX_INT@h */
         mtspr   SPRN_HDEC,r8