KVM: PPC: Book3S HV: Context-switch new POWER8 SPRs

This adds fields to the struct kvm_vcpu_arch to store the new
guest-accessible SPRs on POWER8, adds code to the get/set_one_reg
functions to allow userspace to access this state, and adds code to
the guest entry and exit to context-switch these SPRs between host
and guest.

Note that DPDES (Directed Privileged Doorbell Exception State) is
shared between threads on a core; hence we store it in struct
kvmppc_vcore and have the master thread save and restore it.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>

2 files changed, 296 insertions, 2 deletions

diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 7da53cd215db..5b08ddf91d2d 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -800,7 +800,7 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
         case KVM_REG_PPC_UAMOR:
                 *val = get_reg_val(id, vcpu->arch.uamor);
                 break;
-        case KVM_REG_PPC_MMCR0 ... KVM_REG_PPC_MMCRA:
+        case KVM_REG_PPC_MMCR0 ... KVM_REG_PPC_MMCRS:
                 i = id - KVM_REG_PPC_MMCR0;
                 *val = get_reg_val(id, vcpu->arch.mmcr[i]);
                 break;
@@ -808,12 +808,85 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
                 i = id - KVM_REG_PPC_PMC1;
                 *val = get_reg_val(id, vcpu->arch.pmc[i]);
                 break;
+        case KVM_REG_PPC_SPMC1 ... KVM_REG_PPC_SPMC2:
+                i = id - KVM_REG_PPC_SPMC1;
+                *val = get_reg_val(id, vcpu->arch.spmc[i]);
+                break;
         case KVM_REG_PPC_SIAR:
                 *val = get_reg_val(id, vcpu->arch.siar);
                 break;
         case KVM_REG_PPC_SDAR:
                 *val = get_reg_val(id, vcpu->arch.sdar);
                 break;
+        case KVM_REG_PPC_SIER:
+                *val = get_reg_val(id, vcpu->arch.sier);
+                break;
+        case KVM_REG_PPC_IAMR:
+                *val = get_reg_val(id, vcpu->arch.iamr);
+                break;
+        case KVM_REG_PPC_TFHAR:
+                *val = get_reg_val(id, vcpu->arch.tfhar);
+                break;
+        case KVM_REG_PPC_TFIAR:
+                *val = get_reg_val(id, vcpu->arch.tfiar);
+                break;
+        case KVM_REG_PPC_TEXASR:
+                *val = get_reg_val(id, vcpu->arch.texasr);
+                break;
+        case KVM_REG_PPC_FSCR:
+                *val = get_reg_val(id, vcpu->arch.fscr);
+                break;
+        case KVM_REG_PPC_PSPB:
+                *val = get_reg_val(id, vcpu->arch.pspb);
+                break;
+        case KVM_REG_PPC_EBBHR:
+                *val = get_reg_val(id, vcpu->arch.ebbhr);
+                break;
+        case KVM_REG_PPC_EBBRR:
+                *val = get_reg_val(id, vcpu->arch.ebbrr);
+                break;
+        case KVM_REG_PPC_BESCR:
+                *val = get_reg_val(id, vcpu->arch.bescr);
+                break;
+        case KVM_REG_PPC_TAR:
+                *val = get_reg_val(id, vcpu->arch.tar);
+                break;
+        case KVM_REG_PPC_DPDES:
+                *val = get_reg_val(id, vcpu->arch.vcore->dpdes);
+                break;
+        case KVM_REG_PPC_DAWR:
+                *val = get_reg_val(id, vcpu->arch.dawr);
+                break;
+        case KVM_REG_PPC_DAWRX:
+                *val = get_reg_val(id, vcpu->arch.dawrx);
+                break;
+        case KVM_REG_PPC_CIABR:
+                *val = get_reg_val(id, vcpu->arch.ciabr);
+                break;
+        case KVM_REG_PPC_IC:
+                *val = get_reg_val(id, vcpu->arch.ic);
+                break;
+        case KVM_REG_PPC_VTB:
+                *val = get_reg_val(id, vcpu->arch.vtb);
+                break;
+        case KVM_REG_PPC_CSIGR:
+                *val = get_reg_val(id, vcpu->arch.csigr);
+                break;
+        case KVM_REG_PPC_TACR:
+                *val = get_reg_val(id, vcpu->arch.tacr);
+                break;
+        case KVM_REG_PPC_TCSCR:
+                *val = get_reg_val(id, vcpu->arch.tcscr);
+                break;
+        case KVM_REG_PPC_PID:
+                *val = get_reg_val(id, vcpu->arch.pid);
+                break;
+        case KVM_REG_PPC_ACOP:
+                *val = get_reg_val(id, vcpu->arch.acop);
+                break;
+        case KVM_REG_PPC_WORT:
+                *val = get_reg_val(id, vcpu->arch.wort);
+                break;
         case KVM_REG_PPC_VPA_ADDR:
                 spin_lock(&vcpu->arch.vpa_update_lock);
                 *val = get_reg_val(id, vcpu->arch.vpa.next_gpa);
@@ -882,7 +955,7 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
         case KVM_REG_PPC_UAMOR:
                 vcpu->arch.uamor = set_reg_val(id, *val);
                 break;
-        case KVM_REG_PPC_MMCR0 ... KVM_REG_PPC_MMCRA:
+        case KVM_REG_PPC_MMCR0 ... KVM_REG_PPC_MMCRS:
                 i = id - KVM_REG_PPC_MMCR0;
                 vcpu->arch.mmcr[i] = set_reg_val(id, *val);
                 break;
@@ -890,12 +963,88 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
                 i = id - KVM_REG_PPC_PMC1;
                 vcpu->arch.pmc[i] = set_reg_val(id, *val);
                 break;
+        case KVM_REG_PPC_SPMC1 ... KVM_REG_PPC_SPMC2:
+                i = id - KVM_REG_PPC_SPMC1;
+                vcpu->arch.spmc[i] = set_reg_val(id, *val);
+                break;
         case KVM_REG_PPC_SIAR:
                 vcpu->arch.siar = set_reg_val(id, *val);
                 break;
         case KVM_REG_PPC_SDAR:
                 vcpu->arch.sdar = set_reg_val(id, *val);
                 break;
+        case KVM_REG_PPC_SIER:
+                vcpu->arch.sier = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_IAMR:
+                vcpu->arch.iamr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TFHAR:
+                vcpu->arch.tfhar = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TFIAR:
+                vcpu->arch.tfiar = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TEXASR:
+                vcpu->arch.texasr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_FSCR:
+                vcpu->arch.fscr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_PSPB:
+                vcpu->arch.pspb = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_EBBHR:
+                vcpu->arch.ebbhr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_EBBRR:
+                vcpu->arch.ebbrr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_BESCR:
+                vcpu->arch.bescr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TAR:
+                vcpu->arch.tar = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_DPDES:
+                vcpu->arch.vcore->dpdes = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_DAWR:
+                vcpu->arch.dawr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_DAWRX:
+                vcpu->arch.dawrx = set_reg_val(id, *val) & ~DAWRX_HYP;
+                break;
+        case KVM_REG_PPC_CIABR:
+                vcpu->arch.ciabr = set_reg_val(id, *val);
+                /* Don't allow setting breakpoints in hypervisor code */
+                if ((vcpu->arch.ciabr & CIABR_PRIV) == CIABR_PRIV_HYPER)
+                        vcpu->arch.ciabr &= ~CIABR_PRIV;        /* disable */
+                break;
+        case KVM_REG_PPC_IC:
+                vcpu->arch.ic = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_VTB:
+                vcpu->arch.vtb = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_CSIGR:
+                vcpu->arch.csigr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TACR:
+                vcpu->arch.tacr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_TCSCR:
+                vcpu->arch.tcscr = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_PID:
+                vcpu->arch.pid = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_ACOP:
+                vcpu->arch.acop = set_reg_val(id, *val);
+                break;
+        case KVM_REG_PPC_WORT:
+                vcpu->arch.wort = set_reg_val(id, *val);
+                break;
         case KVM_REG_PPC_VPA_ADDR:
                 addr = set_reg_val(id, *val);
                 r = -EINVAL;
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 8bbe91bdb6da..691dd1ef555b 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -460,6 +460,13 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
         beq     38f
         mtspr   SPRN_PCR, r7
 38:
+
+BEGIN_FTR_SECTION
+        /* DPDES is shared between threads */
+        ld      r8, VCORE_DPDES(r5)
+        mtspr   SPRN_DPDES, r8
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
+
         li      r0,1
         stb     r0,VCORE_IN_GUEST(r5)   /* signal secondaries to continue */
         b       10f
@@ -659,6 +666,18 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
         mtspr   SPRN_MMCRA, r6
         mtspr   SPRN_SIAR, r7
         mtspr   SPRN_SDAR, r8
+BEGIN_FTR_SECTION
+        ld      r5, VCPU_MMCR + 24(r4)
+        ld      r6, VCPU_SIER(r4)
+        lwz     r7, VCPU_PMC + 24(r4)
+        lwz     r8, VCPU_PMC + 28(r4)
+        ld      r9, VCPU_MMCR + 32(r4)
+        mtspr   SPRN_MMCR2, r5
+        mtspr   SPRN_SIER, r6
+        mtspr   SPRN_SPMC1, r7
+        mtspr   SPRN_SPMC2, r8
+        mtspr   SPRN_MMCRS, r9
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
         mtspr   SPRN_MMCR0, r3
         isync
 
@@ -690,6 +709,61 @@ BEGIN_FTR_SECTION
         mtspr   SPRN_DSCR, r5
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
 
+BEGIN_FTR_SECTION
+        /* Skip next section on POWER7 or PPC970 */
+        b       8f
+END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
+        /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
+        mfmsr   r8
+        li      r0, 1
+        rldimi  r8, r0, MSR_TM_LG, 63-MSR_TM_LG
+        mtmsrd  r8
+
+        /* Load up POWER8-specific registers */
+        ld      r5, VCPU_IAMR(r4)
+        lwz     r6, VCPU_PSPB(r4)
+        ld      r7, VCPU_FSCR(r4)
+        mtspr   SPRN_IAMR, r5
+        mtspr   SPRN_PSPB, r6
+        mtspr   SPRN_FSCR, r7
+        ld      r5, VCPU_DAWR(r4)
+        ld      r6, VCPU_DAWRX(r4)
+        ld      r7, VCPU_CIABR(r4)
+        ld      r8, VCPU_TAR(r4)
+        mtspr   SPRN_DAWR, r5
+        mtspr   SPRN_DAWRX, r6
+        mtspr   SPRN_CIABR, r7
+        mtspr   SPRN_TAR, r8
+        ld      r5, VCPU_IC(r4)
+        ld      r6, VCPU_VTB(r4)
+        mtspr   SPRN_IC, r5
+        mtspr   SPRN_VTB, r6
+        ld      r5, VCPU_TFHAR(r4)
+        ld      r6, VCPU_TFIAR(r4)
+        ld      r7, VCPU_TEXASR(r4)
+        ld      r8, VCPU_EBBHR(r4)
+        mtspr   SPRN_TFHAR, r5
+        mtspr   SPRN_TFIAR, r6
+        mtspr   SPRN_TEXASR, r7
+        mtspr   SPRN_EBBHR, r8
+        ld      r5, VCPU_EBBRR(r4)
+        ld      r6, VCPU_BESCR(r4)
+        ld      r7, VCPU_CSIGR(r4)
+        ld      r8, VCPU_TACR(r4)
+        mtspr   SPRN_EBBRR, r5
+        mtspr   SPRN_BESCR, r6
+        mtspr   SPRN_CSIGR, r7
+        mtspr   SPRN_TACR, r8
+        ld      r5, VCPU_TCSCR(r4)
+        ld      r6, VCPU_ACOP(r4)
+        lwz     r7, VCPU_GUEST_PID(r4)
+        ld      r8, VCPU_WORT(r4)
+        mtspr   SPRN_TCSCR, r5
+        mtspr   SPRN_ACOP, r6
+        mtspr   SPRN_PID, r7
+        mtspr   SPRN_WORT, r8
+8:
+
         /*
          * Set the decrementer to the guest decrementer.
          */
@@ -1081,6 +1155,54 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_201)
         add     r5,r5,r6
         std     r5,VCPU_DEC_EXPIRES(r9)
 
+BEGIN_FTR_SECTION
+        b       8f
+END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
+        /* Turn on TM so we can access TFHAR/TFIAR/TEXASR */
+        mfmsr   r8
+        li      r0, 1
+        rldimi  r8, r0, MSR_TM_LG, 63-MSR_TM_LG
+        mtmsrd  r8
+
+        /* Save POWER8-specific registers */
+        mfspr   r5, SPRN_IAMR
+        mfspr   r6, SPRN_PSPB
+        mfspr   r7, SPRN_FSCR
+        std     r5, VCPU_IAMR(r9)
+        stw     r6, VCPU_PSPB(r9)
+        std     r7, VCPU_FSCR(r9)
+        mfspr   r5, SPRN_IC
+        mfspr   r6, SPRN_VTB
+        mfspr   r7, SPRN_TAR
+        std     r5, VCPU_IC(r9)
+        std     r6, VCPU_VTB(r9)
+        std     r7, VCPU_TAR(r9)
+        mfspr   r5, SPRN_TFHAR
+        mfspr   r6, SPRN_TFIAR
+        mfspr   r7, SPRN_TEXASR
+        mfspr   r8, SPRN_EBBHR
+        std     r5, VCPU_TFHAR(r9)
+        std     r6, VCPU_TFIAR(r9)
+        std     r7, VCPU_TEXASR(r9)
+        std     r8, VCPU_EBBHR(r9)
+        mfspr   r5, SPRN_EBBRR
+        mfspr   r6, SPRN_BESCR
+        mfspr   r7, SPRN_CSIGR
+        mfspr   r8, SPRN_TACR
+        std     r5, VCPU_EBBRR(r9)
+        std     r6, VCPU_BESCR(r9)
+        std     r7, VCPU_CSIGR(r9)
+        std     r8, VCPU_TACR(r9)
+        mfspr   r5, SPRN_TCSCR
+        mfspr   r6, SPRN_ACOP
+        mfspr   r7, SPRN_PID
+        mfspr   r8, SPRN_WORT
+        std     r5, VCPU_TCSCR(r9)
+        std     r6, VCPU_ACOP(r9)
+        stw     r7, VCPU_GUEST_PID(r9)
+        std     r8, VCPU_WORT(r9)
+8:
+
         /* Save and reset AMR and UAMOR before turning on the MMU */
 BEGIN_FTR_SECTION
         mfspr   r5,SPRN_AMR
@@ -1190,6 +1312,20 @@ BEGIN_FTR_SECTION
         stw     r10, VCPU_PMC + 24(r9)
         stw     r11, VCPU_PMC + 28(r9)
 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
+BEGIN_FTR_SECTION
+        mfspr   r4, SPRN_MMCR2
+        mfspr   r5, SPRN_SIER
+        mfspr   r6, SPRN_SPMC1
+        mfspr   r7, SPRN_SPMC2
+        mfspr   r8, SPRN_MMCRS
+        std     r4, VCPU_MMCR + 24(r9)
+        std     r5, VCPU_SIER(r9)
+        stw     r6, VCPU_PMC + 24(r9)
+        stw     r7, VCPU_PMC + 28(r9)
+        std     r8, VCPU_MMCR + 32(r9)
+        lis     r4, 0x8000
+        mtspr   SPRN_MMCRS, r4
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
 22:
         /* Clear out SLB */
         li      r5,0
@@ -1290,6 +1426,15 @@ secondary_too_late:
         mtspr   SPRN_LPID,r7
         isync
 
+BEGIN_FTR_SECTION
+        /* DPDES is shared between threads */
+        mfspr   r7, SPRN_DPDES
+        std     r7, VCORE_DPDES(r5)
+        /* clear DPDES so we don't get guest doorbells in the host */
+        li      r8, 0
+        mtspr   SPRN_DPDES, r8
+END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
+
         /* Subtract timebase offset from timebase */
         ld      r8,VCORE_TB_OFFSET(r5)
         cmpdi   r8,0