powerpc: Base support for exceptions using HSRR0/1

Pass the register type to the prolog, also provides alternate "HV"
version of hardware interrupt (0x500) and adjust LPES accordingly

We tag those interrupts by setting bit 0x2 in the trap number

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

2 files changed, 9 insertions, 2 deletions

diff --git a/arch/powerpc/kvm/book3s_rmhandlers.S b/arch/powerpc/kvm/book3s_rmhandlers.S
index b0ff5ff76e25..046e1f3d4432 100644
--- a/arch/powerpc/kvm/book3s_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_rmhandlers.S
@@ -112,6 +112,7 @@ INTERRUPT_TRAMPOLINE	BOOK3S_INTERRUPT_MACHINE_CHECK
 INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_DATA_STORAGE
 INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_INST_STORAGE
 INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_EXTERNAL
+INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_EXTERNAL_HV
 INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_ALIGNMENT
 INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_PROGRAM
 INTERRUPT_TRAMPOLINE    BOOK3S_INTERRUPT_FP_UNAVAIL
diff --git a/arch/powerpc/kvm/book3s_segment.S b/arch/powerpc/kvm/book3s_segment.S
index 7c52ed0b7051..d842795d0f23 100644
--- a/arch/powerpc/kvm/book3s_segment.S
+++ b/arch/powerpc/kvm/book3s_segment.S
@@ -155,9 +155,15 @@ kvmppc_handler_trampoline_exit:
         PPC_LL  r2, (SHADOW_VCPU_OFF + SVCPU_HOST_R2)(r13)
 
         /* Save guest PC and MSR */
-        mfsrr0  r3
+        andi.   r0,r12,0x2
+        beq     1f
+        mfspr   r3,SPRN_HSRR0
+        mfspr   r4,SPRN_HSRR1
+        andi.   r12,r12,0x3ffd
+        b       2f
+1:      mfsrr0  r3
         mfsrr1  r4
-
+2:
         PPC_STL r3, (SHADOW_VCPU_OFF + SVCPU_PC)(r13)
         PPC_STL r4, (SHADOW_VCPU_OFF + SVCPU_SHADOW_SRR1)(r13)