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authorAlexander Graf <agraf@suse.de>2014-04-24 07:46:24 -0400
committerAlexander Graf <agraf@suse.de>2014-05-30 08:26:21 -0400
commit5deb8e7ad8ac7e3fcdfa042acff617f461b361c2 (patch)
treeccfc251ffbadfa4297aefcfe17dee807eba7ce73 /arch/powerpc/kvm/emulate.c
parent2743103f91e20d4c4d4f1a8d00821289c4c6ff62 (diff)
KVM: PPC: Make shared struct aka magic page guest endian
The shared (magic) page is a data structure that contains often used supervisor privileged SPRs accessible via memory to the user to reduce the number of exits we have to take to read/write them. When we actually share this structure with the guest we have to maintain it in guest endianness, because some of the patch tricks only work with native endian load/store operations. Since we only share the structure with either host or guest in little endian on book3s_64 pr mode, we don't have to worry about booke or book3s hv. For booke, the shared struct stays big endian. For book3s_64 hv we maintain the struct in host native endian, since it never gets shared with the guest. For book3s_64 pr we introduce a variable that tells us which endianness the shared struct is in and route every access to it through helper inline functions that evaluate this variable. Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/powerpc/kvm/emulate.c')
-rw-r--r--arch/powerpc/kvm/emulate.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index c2b887be2c29..da86d9ba3476 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
@@ -97,10 +97,10 @@ static int kvmppc_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs)
97 97
98 switch (sprn) { 98 switch (sprn) {
99 case SPRN_SRR0: 99 case SPRN_SRR0:
100 vcpu->arch.shared->srr0 = spr_val; 100 kvmppc_set_srr0(vcpu, spr_val);
101 break; 101 break;
102 case SPRN_SRR1: 102 case SPRN_SRR1:
103 vcpu->arch.shared->srr1 = spr_val; 103 kvmppc_set_srr1(vcpu, spr_val);
104 break; 104 break;
105 105
106 /* XXX We need to context-switch the timebase for 106 /* XXX We need to context-switch the timebase for
@@ -114,16 +114,16 @@ static int kvmppc_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, int rs)
114 break; 114 break;
115 115
116 case SPRN_SPRG0: 116 case SPRN_SPRG0:
117 vcpu->arch.shared->sprg0 = spr_val; 117 kvmppc_set_sprg0(vcpu, spr_val);
118 break; 118 break;
119 case SPRN_SPRG1: 119 case SPRN_SPRG1:
120 vcpu->arch.shared->sprg1 = spr_val; 120 kvmppc_set_sprg1(vcpu, spr_val);
121 break; 121 break;
122 case SPRN_SPRG2: 122 case SPRN_SPRG2:
123 vcpu->arch.shared->sprg2 = spr_val; 123 kvmppc_set_sprg2(vcpu, spr_val);
124 break; 124 break;
125 case SPRN_SPRG3: 125 case SPRN_SPRG3:
126 vcpu->arch.shared->sprg3 = spr_val; 126 kvmppc_set_sprg3(vcpu, spr_val);
127 break; 127 break;
128 128
129 /* PIR can legally be written, but we ignore it */ 129 /* PIR can legally be written, but we ignore it */
@@ -150,10 +150,10 @@ static int kvmppc_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt)
150 150
151 switch (sprn) { 151 switch (sprn) {
152 case SPRN_SRR0: 152 case SPRN_SRR0:
153 spr_val = vcpu->arch.shared->srr0; 153 spr_val = kvmppc_get_srr0(vcpu);
154 break; 154 break;
155 case SPRN_SRR1: 155 case SPRN_SRR1:
156 spr_val = vcpu->arch.shared->srr1; 156 spr_val = kvmppc_get_srr1(vcpu);
157 break; 157 break;
158 case SPRN_PVR: 158 case SPRN_PVR:
159 spr_val = vcpu->arch.pvr; 159 spr_val = vcpu->arch.pvr;
@@ -173,16 +173,16 @@ static int kvmppc_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt)
173 break; 173 break;
174 174
175 case SPRN_SPRG0: 175 case SPRN_SPRG0:
176 spr_val = vcpu->arch.shared->sprg0; 176 spr_val = kvmppc_get_sprg0(vcpu);
177 break; 177 break;
178 case SPRN_SPRG1: 178 case SPRN_SPRG1:
179 spr_val = vcpu->arch.shared->sprg1; 179 spr_val = kvmppc_get_sprg1(vcpu);
180 break; 180 break;
181 case SPRN_SPRG2: 181 case SPRN_SPRG2:
182 spr_val = vcpu->arch.shared->sprg2; 182 spr_val = kvmppc_get_sprg2(vcpu);
183 break; 183 break;
184 case SPRN_SPRG3: 184 case SPRN_SPRG3:
185 spr_val = vcpu->arch.shared->sprg3; 185 spr_val = kvmppc_get_sprg3(vcpu);
186 break; 186 break;
187 /* Note: SPRG4-7 are user-readable, so we don't get 187 /* Note: SPRG4-7 are user-readable, so we don't get
188 * a trap. */ 188 * a trap. */