diff options
author | Alexander Graf <agraf@suse.de> | 2012-05-09 21:58:50 -0400 |
---|---|---|
committer | Alexander Graf <agraf@suse.de> | 2012-05-16 09:02:11 -0400 |
commit | 32c7dbfd479e73684b0d23fcb0a5cb04f19d86f4 (patch) | |
tree | 6b64efd4aed00c5954db0e7fdfef90eb67753a98 /arch/powerpc/kvm/book3s_segment.S | |
parent | 56e13dbae3eddb1648e6e94ae251c83cdc8304e0 (diff) |
KVM: PPC: Book3S: PR: Fix hsrr code
When jumping back into the kernel to code that knows that it would be
using HSRR registers instead of SRR registers, we need to make sure we
pass it all information on where to jump to in HSRR registers.
Unfortunately, we used r10 to store the information to distinguish between
the HSRR and SRR case. That register got clobbered in between though,
rendering the later comparison invalid.
Instead, let's use cr1 to store this information. That way we don't
need yet another register and everyone's happy.
This fixes PR KVM on POWER7 bare metal for me.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/powerpc/kvm/book3s_segment.S')
-rw-r--r-- | arch/powerpc/kvm/book3s_segment.S | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/powerpc/kvm/book3s_segment.S b/arch/powerpc/kvm/book3s_segment.S index 87cfc1def241..6e6e9cef34a8 100644 --- a/arch/powerpc/kvm/book3s_segment.S +++ b/arch/powerpc/kvm/book3s_segment.S | |||
@@ -197,8 +197,8 @@ kvmppc_interrupt: | |||
197 | /* Save guest PC and MSR */ | 197 | /* Save guest PC and MSR */ |
198 | #ifdef CONFIG_PPC64 | 198 | #ifdef CONFIG_PPC64 |
199 | BEGIN_FTR_SECTION | 199 | BEGIN_FTR_SECTION |
200 | mr r10, r12 | 200 | andi. r0, r12, 0x2 |
201 | andi. r0,r12,0x2 | 201 | cmpwi cr1, r0, 0 |
202 | beq 1f | 202 | beq 1f |
203 | mfspr r3,SPRN_HSRR0 | 203 | mfspr r3,SPRN_HSRR0 |
204 | mfspr r4,SPRN_HSRR1 | 204 | mfspr r4,SPRN_HSRR1 |
@@ -345,8 +345,7 @@ no_dcbz32_off: | |||
345 | 345 | ||
346 | #ifdef CONFIG_PPC64 | 346 | #ifdef CONFIG_PPC64 |
347 | BEGIN_FTR_SECTION | 347 | BEGIN_FTR_SECTION |
348 | andi. r0,r10,0x2 | 348 | beq cr1, 1f |
349 | beq 1f | ||
350 | mtspr SPRN_HSRR1, r6 | 349 | mtspr SPRN_HSRR1, r6 |
351 | mtspr SPRN_HSRR0, r8 | 350 | mtspr SPRN_HSRR0, r8 |
352 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) | 351 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |