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authorPaul Mackerras <paulus@samba.org>2013-09-20 00:52:44 -0400
committerAlexander Graf <agraf@suse.de>2013-10-17 08:45:03 -0400
commita4a0f2524acc2c602cadd8e743be19d86f3a746b (patch)
tree582fc20dbf59fbbc1eddc2356b1704e5df2085f2 /arch/powerpc/kvm/book3s_pr.c
parenta2d56020d1d91934e7bb3e7c8a5a3b5921ce121b (diff)
KVM: PPC: Book3S PR: Allow guest to use 64k pages
This adds the code to interpret 64k HPTEs in the guest hashed page table (HPT), 64k SLB entries, and to tell the guest about 64k pages in kvm_vm_ioctl_get_smmu_info(). Guest 64k pages are still shadowed by 4k pages. This also adds another hash table to the four we have already in book3s_mmu_hpte.c to allow us to find all the PTEs that we have instantiated that match a given 64k guest page. The tlbie instruction changed starting with POWER6 to use a bit in the RB operand to indicate large page invalidations, and to use other RB bits to indicate the base and actual page sizes and the segment size. 64k pages came in slightly earlier, with POWER5++. We use one bit in vcpu->arch.hflags to indicate that the emulated cpu supports 64k pages, and another to indicate that it has the new tlbie definition. The KVM_PPC_GET_SMMU_INFO ioctl presents a bit of a problem, because the MMU capabilities depend on which CPU model we're emulating, but it is a VM ioctl not a VCPU ioctl and therefore doesn't get passed a VCPU fd. In addition, commonly-used userspace (QEMU) calls it before setting the PVR for any VCPU. Therefore, as a best effort we look at the first vcpu in the VM and return 64k pages or not depending on its capabilities. We also make the PVR default to the host PVR on recent CPUs that support 1TB segments (and therefore multiple page sizes as well) so that KVM_PPC_GET_SMMU_INFO will include 64k page and 1TB segment support on those CPUs. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/powerpc/kvm/book3s_pr.c')
-rw-r--r--arch/powerpc/kvm/book3s_pr.c58
1 files changed, 52 insertions, 6 deletions
diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c
index 228a9baffd9e..6cc99583ed39 100644
--- a/arch/powerpc/kvm/book3s_pr.c
+++ b/arch/powerpc/kvm/book3s_pr.c
@@ -306,6 +306,23 @@ void kvmppc_set_pvr(struct kvm_vcpu *vcpu, u32 pvr)
306 if (!strcmp(cur_cpu_spec->platform, "ppc-cell-be")) 306 if (!strcmp(cur_cpu_spec->platform, "ppc-cell-be"))
307 to_book3s(vcpu)->msr_mask &= ~(MSR_FE0 | MSR_FE1); 307 to_book3s(vcpu)->msr_mask &= ~(MSR_FE0 | MSR_FE1);
308 308
309 /*
310 * If they're asking for POWER6 or later, set the flag
311 * indicating that we can do multiple large page sizes
312 * and 1TB segments.
313 * Also set the flag that indicates that tlbie has the large
314 * page bit in the RB operand instead of the instruction.
315 */
316 switch (PVR_VER(pvr)) {
317 case PVR_POWER6:
318 case PVR_POWER7:
319 case PVR_POWER7p:
320 case PVR_POWER8:
321 vcpu->arch.hflags |= BOOK3S_HFLAG_MULTI_PGSIZE |
322 BOOK3S_HFLAG_NEW_TLBIE;
323 break;
324 }
325
309#ifdef CONFIG_PPC_BOOK3S_32 326#ifdef CONFIG_PPC_BOOK3S_32
310 /* 32 bit Book3S always has 32 byte dcbz */ 327 /* 32 bit Book3S always has 32 byte dcbz */
311 vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32; 328 vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
@@ -1130,8 +1147,14 @@ struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id)
1130 vcpu->arch.shared = (void *)(p + PAGE_SIZE - 4096); 1147 vcpu->arch.shared = (void *)(p + PAGE_SIZE - 4096);
1131 1148
1132#ifdef CONFIG_PPC_BOOK3S_64 1149#ifdef CONFIG_PPC_BOOK3S_64
1133 /* default to book3s_64 (970fx) */ 1150 /*
1151 * Default to the same as the host if we're on sufficiently
1152 * recent machine that we have 1TB segments;
1153 * otherwise default to PPC970FX.
1154 */
1134 vcpu->arch.pvr = 0x3C0301; 1155 vcpu->arch.pvr = 0x3C0301;
1156 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1157 vcpu->arch.pvr = mfspr(SPRN_PVR);
1135#else 1158#else
1136 /* default to book3s_32 (750) */ 1159 /* default to book3s_32 (750) */
1137 vcpu->arch.pvr = 0x84202; 1160 vcpu->arch.pvr = 0x84202;
@@ -1317,7 +1340,10 @@ out:
1317#ifdef CONFIG_PPC64 1340#ifdef CONFIG_PPC64
1318int kvm_vm_ioctl_get_smmu_info(struct kvm *kvm, struct kvm_ppc_smmu_info *info) 1341int kvm_vm_ioctl_get_smmu_info(struct kvm *kvm, struct kvm_ppc_smmu_info *info)
1319{ 1342{
1320 info->flags = KVM_PPC_1T_SEGMENTS; 1343 long int i;
1344 struct kvm_vcpu *vcpu;
1345
1346 info->flags = 0;
1321 1347
1322 /* SLB is always 64 entries */ 1348 /* SLB is always 64 entries */
1323 info->slb_size = 64; 1349 info->slb_size = 64;
@@ -1328,11 +1354,31 @@ int kvm_vm_ioctl_get_smmu_info(struct kvm *kvm, struct kvm_ppc_smmu_info *info)
1328 info->sps[0].enc[0].page_shift = 12; 1354 info->sps[0].enc[0].page_shift = 12;
1329 info->sps[0].enc[0].pte_enc = 0; 1355 info->sps[0].enc[0].pte_enc = 0;
1330 1356
1357 /*
1358 * 64k large page size.
1359 * We only want to put this in if the CPUs we're emulating
1360 * support it, but unfortunately we don't have a vcpu easily
1361 * to hand here to test. Just pick the first vcpu, and if
1362 * that doesn't exist yet, report the minimum capability,
1363 * i.e., no 64k pages.
1364 * 1T segment support goes along with 64k pages.
1365 */
1366 i = 1;
1367 vcpu = kvm_get_vcpu(kvm, 0);
1368 if (vcpu && (vcpu->arch.hflags & BOOK3S_HFLAG_MULTI_PGSIZE)) {
1369 info->flags = KVM_PPC_1T_SEGMENTS;
1370 info->sps[i].page_shift = 16;
1371 info->sps[i].slb_enc = SLB_VSID_L | SLB_VSID_LP_01;
1372 info->sps[i].enc[0].page_shift = 16;
1373 info->sps[i].enc[0].pte_enc = 1;
1374 ++i;
1375 }
1376
1331 /* Standard 16M large page size segment */ 1377 /* Standard 16M large page size segment */
1332 info->sps[1].page_shift = 24; 1378 info->sps[i].page_shift = 24;
1333 info->sps[1].slb_enc = SLB_VSID_L; 1379 info->sps[i].slb_enc = SLB_VSID_L;
1334 info->sps[1].enc[0].page_shift = 24; 1380 info->sps[i].enc[0].page_shift = 24;
1335 info->sps[1].enc[0].pte_enc = 0; 1381 info->sps[i].enc[0].pte_enc = 0;
1336 1382
1337 return 0; 1383 return 0;
1338} 1384}