Merge branch 'sched/urgent' into sched/core

Merge reason: Merge dependent fix, update to latest -rc.

Signed-off-by: Ingo Molnar <mingo@elte.hu>

1 files changed, 21 insertions, 1 deletions

diff --git a/arch/powerpc/kvm/book3s_64_mmu.c b/arch/powerpc/kvm/book3s_64_mmu.c
index 5598f88f142e..e4beeb371a73 100644
--- a/arch/powerpc/kvm/book3s_64_mmu.c
+++ b/arch/powerpc/kvm/book3s_64_mmu.c
@@ -390,6 +390,26 @@ static void kvmppc_mmu_book3s_64_mtsrin(struct kvm_vcpu *vcpu, u32 srnum,
 {
         u64 rb = 0, rs = 0;
 
+        /*
+         * According to Book3 2.01 mtsrin is implemented as:
+         *
+         * The SLB entry specified by (RB)32:35 is loaded from register
+         * RS, as follows.
+         *
+         * SLBE Bit     Source                  SLB Field
+         *
+         * 0:31         0x0000_0000             ESID-0:31
+         * 32:35        (RB)32:35               ESID-32:35
+         * 36           0b1                     V
+         * 37:61        0x00_0000|| 0b0         VSID-0:24
+         * 62:88        (RS)37:63               VSID-25:51
+         * 89:91        (RS)33:35               Ks Kp N
+         * 92           (RS)36                  L ((RS)36 must be 0b0)
+         * 93           0b0                     C
+         */
+
+        dprintk("KVM MMU: mtsrin(0x%x, 0x%lx)\n", srnum, value);
+
         /* ESID = srnum */
         rb |= (srnum & 0xf) << 28;
         /* Set the valid bit */
@@ -400,7 +420,7 @@ static void kvmppc_mmu_book3s_64_mtsrin(struct kvm_vcpu *vcpu, u32 srnum,
         /* VSID = VSID */
         rs |= (value & 0xfffffff) << 12;
         /* flags = flags */
-        rs |= ((value >> 27) & 0xf) << 9;
+        rs |= ((value >> 28) & 0x7) << 9;
 
         kvmppc_mmu_book3s_64_slbmte(vcpu, rs, rb);
 }