diff options
author | Alexander Graf <agraf@suse.de> | 2010-03-24 16:48:24 -0400 |
---|---|---|
committer | Avi Kivity <avi@redhat.com> | 2010-05-17 05:17:01 -0400 |
commit | c664876c6d88ff8c8e93ee05c0bbdc3e4c2af488 (patch) | |
tree | d478322acafbae0971e7f0dd0cab31ed7299c463 /arch/powerpc/kvm/book3s_64_emulate.c | |
parent | a56cf347c21b21d52db127672cf1edf5dd724a4b (diff) |
KVM: PPC: Implement mfsr emulation
We emulate the mfsrin instruction already, that passes the SR number
in a register value. But we lacked support for mfsr that encoded the
SR number in the opcode.
So let's implement it.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
Diffstat (limited to 'arch/powerpc/kvm/book3s_64_emulate.c')
-rw-r--r-- | arch/powerpc/kvm/book3s_64_emulate.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/powerpc/kvm/book3s_64_emulate.c b/arch/powerpc/kvm/book3s_64_emulate.c index c9892140dd02..8d7a78d87eff 100644 --- a/arch/powerpc/kvm/book3s_64_emulate.c +++ b/arch/powerpc/kvm/book3s_64_emulate.c | |||
@@ -35,6 +35,7 @@ | |||
35 | #define OP_31_XOP_SLBMTE 402 | 35 | #define OP_31_XOP_SLBMTE 402 |
36 | #define OP_31_XOP_SLBIE 434 | 36 | #define OP_31_XOP_SLBIE 434 |
37 | #define OP_31_XOP_SLBIA 498 | 37 | #define OP_31_XOP_SLBIA 498 |
38 | #define OP_31_XOP_MFSR 595 | ||
38 | #define OP_31_XOP_MFSRIN 659 | 39 | #define OP_31_XOP_MFSRIN 659 |
39 | #define OP_31_XOP_SLBMFEV 851 | 40 | #define OP_31_XOP_SLBMFEV 851 |
40 | #define OP_31_XOP_EIOIO 854 | 41 | #define OP_31_XOP_EIOIO 854 |
@@ -90,6 +91,18 @@ int kvmppc_core_emulate_op(struct kvm_run *run, struct kvm_vcpu *vcpu, | |||
90 | case OP_31_XOP_MTMSR: | 91 | case OP_31_XOP_MTMSR: |
91 | kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, get_rs(inst))); | 92 | kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, get_rs(inst))); |
92 | break; | 93 | break; |
94 | case OP_31_XOP_MFSR: | ||
95 | { | ||
96 | int srnum; | ||
97 | |||
98 | srnum = kvmppc_get_field(inst, 12 + 32, 15 + 32); | ||
99 | if (vcpu->arch.mmu.mfsrin) { | ||
100 | u32 sr; | ||
101 | sr = vcpu->arch.mmu.mfsrin(vcpu, srnum); | ||
102 | kvmppc_set_gpr(vcpu, get_rt(inst), sr); | ||
103 | } | ||
104 | break; | ||
105 | } | ||
93 | case OP_31_XOP_MFSRIN: | 106 | case OP_31_XOP_MFSRIN: |
94 | { | 107 | { |
95 | int srnum; | 108 | int srnum; |