diff options
author | Hollis Blanchard <hollisb@us.ibm.com> | 2009-01-04 14:51:09 -0500 |
---|---|---|
committer | Avi Kivity <avi@redhat.com> | 2009-03-24 05:03:01 -0400 |
commit | f5d0906b5bafd7faea553ed1cc92bd06755b66b9 (patch) | |
tree | 3de9c4e3d678fce1940e4b76294fadfea5b4fc6a /arch/powerpc/kvm/44x.c | |
parent | 269e05e48502f1cc06802e9fba90f5100dd6bb0d (diff) |
KVM: ppc: remove debug support broken by KVM debug rewrite
After the rewrite of KVM's debug support, this code doesn't even build any
more.
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
Diffstat (limited to 'arch/powerpc/kvm/44x.c')
-rw-r--r-- | arch/powerpc/kvm/44x.c | 66 |
1 files changed, 0 insertions, 66 deletions
diff --git a/arch/powerpc/kvm/44x.c b/arch/powerpc/kvm/44x.c index 8383603dd8a4..0cef809cec21 100644 --- a/arch/powerpc/kvm/44x.c +++ b/arch/powerpc/kvm/44x.c | |||
@@ -28,72 +28,6 @@ | |||
28 | 28 | ||
29 | #include "44x_tlb.h" | 29 | #include "44x_tlb.h" |
30 | 30 | ||
31 | /* Note: clearing MSR[DE] just means that the debug interrupt will not be | ||
32 | * delivered *immediately*. Instead, it simply sets the appropriate DBSR bits. | ||
33 | * If those DBSR bits are still set when MSR[DE] is re-enabled, the interrupt | ||
34 | * will be delivered as an "imprecise debug event" (which is indicated by | ||
35 | * DBSR[IDE]. | ||
36 | */ | ||
37 | static void kvm44x_disable_debug_interrupts(void) | ||
38 | { | ||
39 | mtmsr(mfmsr() & ~MSR_DE); | ||
40 | } | ||
41 | |||
42 | void kvmppc_core_load_host_debugstate(struct kvm_vcpu *vcpu) | ||
43 | { | ||
44 | kvm44x_disable_debug_interrupts(); | ||
45 | |||
46 | mtspr(SPRN_IAC1, vcpu->arch.host_iac[0]); | ||
47 | mtspr(SPRN_IAC2, vcpu->arch.host_iac[1]); | ||
48 | mtspr(SPRN_IAC3, vcpu->arch.host_iac[2]); | ||
49 | mtspr(SPRN_IAC4, vcpu->arch.host_iac[3]); | ||
50 | mtspr(SPRN_DBCR1, vcpu->arch.host_dbcr1); | ||
51 | mtspr(SPRN_DBCR2, vcpu->arch.host_dbcr2); | ||
52 | mtspr(SPRN_DBCR0, vcpu->arch.host_dbcr0); | ||
53 | mtmsr(vcpu->arch.host_msr); | ||
54 | } | ||
55 | |||
56 | void kvmppc_core_load_guest_debugstate(struct kvm_vcpu *vcpu) | ||
57 | { | ||
58 | struct kvm_guest_debug *dbg = &vcpu->guest_debug; | ||
59 | u32 dbcr0 = 0; | ||
60 | |||
61 | vcpu->arch.host_msr = mfmsr(); | ||
62 | kvm44x_disable_debug_interrupts(); | ||
63 | |||
64 | /* Save host debug register state. */ | ||
65 | vcpu->arch.host_iac[0] = mfspr(SPRN_IAC1); | ||
66 | vcpu->arch.host_iac[1] = mfspr(SPRN_IAC2); | ||
67 | vcpu->arch.host_iac[2] = mfspr(SPRN_IAC3); | ||
68 | vcpu->arch.host_iac[3] = mfspr(SPRN_IAC4); | ||
69 | vcpu->arch.host_dbcr0 = mfspr(SPRN_DBCR0); | ||
70 | vcpu->arch.host_dbcr1 = mfspr(SPRN_DBCR1); | ||
71 | vcpu->arch.host_dbcr2 = mfspr(SPRN_DBCR2); | ||
72 | |||
73 | /* set registers up for guest */ | ||
74 | |||
75 | if (dbg->bp[0]) { | ||
76 | mtspr(SPRN_IAC1, dbg->bp[0]); | ||
77 | dbcr0 |= DBCR0_IAC1 | DBCR0_IDM; | ||
78 | } | ||
79 | if (dbg->bp[1]) { | ||
80 | mtspr(SPRN_IAC2, dbg->bp[1]); | ||
81 | dbcr0 |= DBCR0_IAC2 | DBCR0_IDM; | ||
82 | } | ||
83 | if (dbg->bp[2]) { | ||
84 | mtspr(SPRN_IAC3, dbg->bp[2]); | ||
85 | dbcr0 |= DBCR0_IAC3 | DBCR0_IDM; | ||
86 | } | ||
87 | if (dbg->bp[3]) { | ||
88 | mtspr(SPRN_IAC4, dbg->bp[3]); | ||
89 | dbcr0 |= DBCR0_IAC4 | DBCR0_IDM; | ||
90 | } | ||
91 | |||
92 | mtspr(SPRN_DBCR0, dbcr0); | ||
93 | mtspr(SPRN_DBCR1, 0); | ||
94 | mtspr(SPRN_DBCR2, 0); | ||
95 | } | ||
96 | |||
97 | void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu) | 31 | void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
98 | { | 32 | { |
99 | kvmppc_44x_tlb_load(vcpu); | 33 | kvmppc_44x_tlb_load(vcpu); |