diff options
author | Michael Ellerman <michael@ellerman.id.au> | 2013-04-25 15:28:22 -0400 |
---|---|---|
committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2013-04-26 02:11:06 -0400 |
commit | 240686c1368775b5dc80aae863301189b25f9bfa (patch) | |
tree | ff231854aed343e77fce506d9c93479861971be9 /arch/powerpc/kernel | |
parent | 959c9bdd5828981d3d226873aba930019798fa65 (diff) |
powerpc: Initialise PMU related regs on Power8
For both HV and guest kernels, intialise PMU regs to something sane.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel')
-rw-r--r-- | arch/powerpc/kernel/cpu_setup_power.S | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index 4daa5b799010..e0c419b8d65b 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S | |||
@@ -49,6 +49,7 @@ _GLOBAL(__restore_cpu_power7) | |||
49 | _GLOBAL(__setup_cpu_power8) | 49 | _GLOBAL(__setup_cpu_power8) |
50 | mflr r11 | 50 | mflr r11 |
51 | bl __init_FSCR | 51 | bl __init_FSCR |
52 | bl __init_PMU | ||
52 | bl __init_hvmode_206 | 53 | bl __init_hvmode_206 |
53 | mtlr r11 | 54 | mtlr r11 |
54 | beqlr | 55 | beqlr |
@@ -59,12 +60,14 @@ _GLOBAL(__setup_cpu_power8) | |||
59 | bl __init_LPCR | 60 | bl __init_LPCR |
60 | bl __init_HFSCR | 61 | bl __init_HFSCR |
61 | bl __init_TLB | 62 | bl __init_TLB |
63 | bl __init_PMU_HV | ||
62 | mtlr r11 | 64 | mtlr r11 |
63 | blr | 65 | blr |
64 | 66 | ||
65 | _GLOBAL(__restore_cpu_power8) | 67 | _GLOBAL(__restore_cpu_power8) |
66 | mflr r11 | 68 | mflr r11 |
67 | bl __init_FSCR | 69 | bl __init_FSCR |
70 | bl __init_PMU | ||
68 | mfmsr r3 | 71 | mfmsr r3 |
69 | rldicl. r0,r3,4,63 | 72 | rldicl. r0,r3,4,63 |
70 | mtlr r11 | 73 | mtlr r11 |
@@ -76,6 +79,7 @@ _GLOBAL(__restore_cpu_power8) | |||
76 | bl __init_LPCR | 79 | bl __init_LPCR |
77 | bl __init_HFSCR | 80 | bl __init_HFSCR |
78 | bl __init_TLB | 81 | bl __init_TLB |
82 | bl __init_PMU_HV | ||
79 | mtlr r11 | 83 | mtlr r11 |
80 | blr | 84 | blr |
81 | 85 | ||
@@ -125,7 +129,7 @@ __init_FSCR: | |||
125 | 129 | ||
126 | __init_HFSCR: | 130 | __init_HFSCR: |
127 | mfspr r3,SPRN_HFSCR | 131 | mfspr r3,SPRN_HFSCR |
128 | ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP | 132 | ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_PM |
129 | mtspr SPRN_HFSCR,r3 | 133 | mtspr SPRN_HFSCR,r3 |
130 | blr | 134 | blr |
131 | 135 | ||
@@ -140,3 +144,18 @@ __init_TLB: | |||
140 | bdnz 2b | 144 | bdnz 2b |
141 | ptesync | 145 | ptesync |
142 | 1: blr | 146 | 1: blr |
147 | |||
148 | __init_PMU_HV: | ||
149 | li r5,0 | ||
150 | mtspr SPRN_MMCRC,r5 | ||
151 | mtspr SPRN_MMCRH,r5 | ||
152 | blr | ||
153 | |||
154 | __init_PMU: | ||
155 | li r5,0 | ||
156 | mtspr SPRN_MMCRS,r5 | ||
157 | mtspr SPRN_MMCRA,r5 | ||
158 | mtspr SPRN_MMCR0,r5 | ||
159 | mtspr SPRN_MMCR1,r5 | ||
160 | mtspr SPRN_MMCR2,r5 | ||
161 | blr | ||