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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-02-17 21:23:30 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-02-17 21:23:30 -0500
commit3b7faeb49e7c35db857b595c389436994ab1275e (patch)
tree973208eb935876ebed9f2baf262ed08351764752 /arch/powerpc/kernel
parent82a0a1cc8f94bc59e5919715bc03fc8353fa770d (diff)
parent96a8bac5895a41b0fb05a6aa7c3fa1ea631a91fe (diff)
Merge commit 'kumar/next' into next
Diffstat (limited to 'arch/powerpc/kernel')
-rw-r--r--arch/powerpc/kernel/entry_32.S6
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S14
2 files changed, 10 insertions, 10 deletions
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 6f7eb7e00c79..301c646d1a7d 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -63,7 +63,7 @@ debug_transfer_to_handler:
63 63
64 .globl crit_transfer_to_handler 64 .globl crit_transfer_to_handler
65crit_transfer_to_handler: 65crit_transfer_to_handler:
66#ifdef CONFIG_FSL_BOOKE 66#ifdef CONFIG_PPC_BOOK3E_MMU
67 mfspr r0,SPRN_MAS0 67 mfspr r0,SPRN_MAS0
68 stw r0,MAS0(r11) 68 stw r0,MAS0(r11)
69 mfspr r0,SPRN_MAS1 69 mfspr r0,SPRN_MAS1
@@ -78,7 +78,7 @@ crit_transfer_to_handler:
78 mfspr r0,SPRN_MAS7 78 mfspr r0,SPRN_MAS7
79 stw r0,MAS7(r11) 79 stw r0,MAS7(r11)
80#endif /* CONFIG_PHYS_64BIT */ 80#endif /* CONFIG_PHYS_64BIT */
81#endif /* CONFIG_FSL_BOOKE */ 81#endif /* CONFIG_PPC_BOOK3E_MMU */
82#ifdef CONFIG_44x 82#ifdef CONFIG_44x
83 mfspr r0,SPRN_MMUCR 83 mfspr r0,SPRN_MMUCR
84 stw r0,MMUCR(r11) 84 stw r0,MMUCR(r11)
@@ -914,7 +914,7 @@ exc_exit_restart_end:
914 mtspr SPRN_##exc_lvl_srr0,r9; \ 914 mtspr SPRN_##exc_lvl_srr0,r9; \
915 mtspr SPRN_##exc_lvl_srr1,r10; 915 mtspr SPRN_##exc_lvl_srr1,r10;
916 916
917#if defined(CONFIG_FSL_BOOKE) 917#if defined(CONFIG_PPC_BOOK3E_MMU)
918#ifdef CONFIG_PHYS_64BIT 918#ifdef CONFIG_PHYS_64BIT
919#define RESTORE_MAS7 \ 919#define RESTORE_MAS7 \
920 lwz r11,MAS7(r1); \ 920 lwz r11,MAS7(r1); \
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 64ecb1603a77..4ea6e1a7e4b9 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -173,7 +173,7 @@ skpinv: addi r6,r6,1 /* Increment */
173 173
174 /* grab and fixup the RPN */ 174 /* grab and fixup the RPN */
175 mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */ 175 mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
176 rlwinm r6,r6,25,27,30 176 rlwinm r6,r6,25,27,31
177 li r8,-1 177 li r8,-1
178 addi r6,r6,10 178 addi r6,r6,10
179 slw r6,r8,r6 /* convert to mask */ 179 slw r6,r8,r6 /* convert to mask */
@@ -199,7 +199,7 @@ skpinv: addi r6,r6,1 /* Increment */
199 xori r6,r4,1 /* Setup TMP mapping in the other Address space */ 199 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
200 slwi r6,r6,12 200 slwi r6,r6,12
201 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h 201 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
202 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l 202 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
203 mtspr SPRN_MAS1,r6 203 mtspr SPRN_MAS1,r6
204 mfspr r6,SPRN_MAS2 204 mfspr r6,SPRN_MAS2
205 li r7,0 /* temp EPN = 0 */ 205 li r7,0 /* temp EPN = 0 */
@@ -257,10 +257,10 @@ skpinv: addi r6,r6,1 /* Increment */
257 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */ 257 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
258 mtspr SPRN_MAS0,r6 258 mtspr SPRN_MAS0,r6
259 lis r6,(MAS1_VALID|MAS1_IPROT)@h 259 lis r6,(MAS1_VALID|MAS1_IPROT)@h
260 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l 260 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
261 mtspr SPRN_MAS1,r6 261 mtspr SPRN_MAS1,r6
262 lis r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@h 262 lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
263 ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@l 263 ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
264 mtspr SPRN_MAS2,r6 264 mtspr SPRN_MAS2,r6
265 mtspr SPRN_MAS3,r8 265 mtspr SPRN_MAS3,r8
266 tlbwe 266 tlbwe
@@ -315,7 +315,7 @@ skpinv: addi r6,r6,1 /* Increment */
315 mtspr SPRN_IVPR,r4 315 mtspr SPRN_IVPR,r4
316 316
317 /* Setup the defaults for TLB entries */ 317 /* Setup the defaults for TLB entries */
318 li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l 318 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
319#ifdef CONFIG_E200 319#ifdef CONFIG_E200
320 oris r2,r2,MAS4_TLBSELD(1)@h 320 oris r2,r2,MAS4_TLBSELD(1)@h
321#endif 321#endif
@@ -1116,7 +1116,7 @@ __secondary_start:
1116 mtspr SPRN_SPRG3,r4 1116 mtspr SPRN_SPRG3,r4
1117 1117
1118 /* Setup the defaults for TLB entries */ 1118 /* Setup the defaults for TLB entries */
1119 li r4,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l 1119 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1120 mtspr SPRN_MAS4,r4 1120 mtspr SPRN_MAS4,r4
1121 1121
1122 /* Jump to start_secondary */ 1122 /* Jump to start_secondary */