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authorAndreas Schwab <schwab@linux-m68k.org>2010-08-21 07:43:20 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2010-09-02 00:07:32 -0400
commit05d77ac90c0d260ae18decd70507dc4f5b71a2cb (patch)
tree84cca10e89f60d8530d9951e8e20931329154ef2 /arch/powerpc/kernel
parent872e439a45ed4a4bd499bc55cb0dffa74027f749 (diff)
powerpc: Remove fpscr use from [kvm_]cvt_{fd,df}
Neither lfs nor stfs touch the fpscr, so remove the restore/save of it around them. Signed-off-by: Andreas Schwab <schwab@linux-m68k.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel')
-rw-r--r--arch/powerpc/kernel/align.c4
-rw-r--r--arch/powerpc/kernel/fpu.S10
2 files changed, 2 insertions, 12 deletions
diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
index b876e989220b..8184ee97e484 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -889,7 +889,7 @@ int fix_alignment(struct pt_regs *regs)
889#ifdef CONFIG_PPC_FPU 889#ifdef CONFIG_PPC_FPU
890 preempt_disable(); 890 preempt_disable();
891 enable_kernel_fp(); 891 enable_kernel_fp();
892 cvt_df(&data.dd, (float *)&data.v[4], &current->thread); 892 cvt_df(&data.dd, (float *)&data.v[4]);
893 preempt_enable(); 893 preempt_enable();
894#else 894#else
895 return 0; 895 return 0;
@@ -933,7 +933,7 @@ int fix_alignment(struct pt_regs *regs)
933#ifdef CONFIG_PPC_FPU 933#ifdef CONFIG_PPC_FPU
934 preempt_disable(); 934 preempt_disable();
935 enable_kernel_fp(); 935 enable_kernel_fp();
936 cvt_fd((float *)&data.v[4], &data.dd, &current->thread); 936 cvt_fd((float *)&data.v[4], &data.dd);
937 preempt_enable(); 937 preempt_enable();
938#else 938#else
939 return 0; 939 return 0;
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index fc8f5b14019c..e86c040ae585 100644
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -163,24 +163,14 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX)
163/* 163/*
164 * These are used in the alignment trap handler when emulating 164 * These are used in the alignment trap handler when emulating
165 * single-precision loads and stores. 165 * single-precision loads and stores.
166 * We restore and save the fpscr so the task gets the same result
167 * and exceptions as if the cpu had performed the load or store.
168 */ 166 */
169 167
170_GLOBAL(cvt_fd) 168_GLOBAL(cvt_fd)
171 lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */
172 MTFSF_L(0)
173 lfs 0,0(r3) 169 lfs 0,0(r3)
174 stfd 0,0(r4) 170 stfd 0,0(r4)
175 mffs 0
176 stfd 0,THREAD_FPSCR(r5) /* save new fpscr value */
177 blr 171 blr
178 172
179_GLOBAL(cvt_df) 173_GLOBAL(cvt_df)
180 lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */
181 MTFSF_L(0)
182 lfd 0,0(r3) 174 lfd 0,0(r3)
183 stfs 0,0(r4) 175 stfs 0,0(r4)
184 mffs 0
185 stfd 0,THREAD_FPSCR(r5) /* save new fpscr value */
186 blr 176 blr