aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/kernel
diff options
context:
space:
mode:
authorPaul Mackerras <paulus@samba.org>2006-09-13 08:08:26 -0400
committerPaul Mackerras <paulus@samba.org>2006-09-13 08:08:26 -0400
commitf007cacffc8870702a1473d83ba5e4922d54e17c (patch)
tree7faa1dbd7ccd2c4536f29852e0fedf7499d90508 /arch/powerpc/kernel
parent2e8e8dacc566cc91cd8707cb092e76c7bbfab178 (diff)
[POWERPC] Fix MMIO ops to provide expected barrier behaviour
This changes the writeX family of functions to have a sync instruction before the MMIO store rather than after, because the generally expected behaviour is that the device receiving the MMIO store can be guaranteed to see the effects of any preceding writes to normal memory. To preserve ordering between writeX and readX, and to preserve ordering between preceding stores and the readX, the readX family of functions have had an sync added before the load. Although writeX followed by spin_unlock is not officially guaranteed to keep the writeX inside the spin-locked region unless an mmiowb() is used, there are currently drivers that depend on the previous behaviour on powerpc, which was that the mmiowb wasn't actually required. Therefore we have a per-cpu flag that is set by writeX, cleared by __raw_spin_lock and mmiowb, and tested by __raw_spin_unlock. If it is set, __raw_spin_unlock does a sync and clears it. This changes both 32-bit and 64-bit readX/writeX. 32-bit already has a sync in __raw_spin_unlock (since lwsync doesn't exist on 32-bit), and thus doesn't need the per-cpu flag. Tested on G5 (PPC970) and POWER5. Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/kernel')
-rw-r--r--arch/powerpc/kernel/misc.S49
1 files changed, 25 insertions, 24 deletions
diff --git a/arch/powerpc/kernel/misc.S b/arch/powerpc/kernel/misc.S
index fc23040d5a26..f770805f1215 100644
--- a/arch/powerpc/kernel/misc.S
+++ b/arch/powerpc/kernel/misc.S
@@ -17,15 +17,6 @@
17 17
18 .text 18 .text
19 19
20#ifdef CONFIG_PPC64
21#define IN_SYNC twi 0,r5,0; isync
22#define EIEIO_32
23#define SYNC_64 sync
24#else /* CONFIG_PPC32 */
25#define IN_SYNC
26#define EIEIO_32 eieio
27#define SYNC_64
28#endif
29/* 20/*
30 * Returns (address we are running at) - (address we were linked at) 21 * Returns (address we are running at) - (address we were linked at)
31 * for use before the text and data are mapped to KERNELBASE. 22 * for use before the text and data are mapped to KERNELBASE.
@@ -70,6 +61,7 @@ _GLOBAL(add_reloc_offset)
70 * The *_ns versions don't do byte-swapping. 61 * The *_ns versions don't do byte-swapping.
71 */ 62 */
72_GLOBAL(_insb) 63_GLOBAL(_insb)
64 sync
73 cmpwi 0,r5,0 65 cmpwi 0,r5,0
74 mtctr r5 66 mtctr r5
75 subi r4,r4,1 67 subi r4,r4,1
@@ -78,7 +70,8 @@ _GLOBAL(_insb)
78 eieio 70 eieio
79 stbu r5,1(r4) 71 stbu r5,1(r4)
80 bdnz 00b 72 bdnz 00b
81 IN_SYNC 73 twi 0,r5,0
74 isync
82 blr 75 blr
83 76
84_GLOBAL(_outsb) 77_GLOBAL(_outsb)
@@ -86,14 +79,15 @@ _GLOBAL(_outsb)
86 mtctr r5 79 mtctr r5
87 subi r4,r4,1 80 subi r4,r4,1
88 blelr- 81 blelr-
82 sync
8900: lbzu r5,1(r4) 8300: lbzu r5,1(r4)
90 stb r5,0(r3) 84 stb r5,0(r3)
91 EIEIO_32
92 bdnz 00b 85 bdnz 00b
93 SYNC_64 86 sync
94 blr 87 blr
95 88
96_GLOBAL(_insw) 89_GLOBAL(_insw)
90 sync
97 cmpwi 0,r5,0 91 cmpwi 0,r5,0
98 mtctr r5 92 mtctr r5
99 subi r4,r4,2 93 subi r4,r4,2
@@ -102,7 +96,8 @@ _GLOBAL(_insw)
102 eieio 96 eieio
103 sthu r5,2(r4) 97 sthu r5,2(r4)
104 bdnz 00b 98 bdnz 00b
105 IN_SYNC 99 twi 0,r5,0
100 isync
106 blr 101 blr
107 102
108_GLOBAL(_outsw) 103_GLOBAL(_outsw)
@@ -110,14 +105,15 @@ _GLOBAL(_outsw)
110 mtctr r5 105 mtctr r5
111 subi r4,r4,2 106 subi r4,r4,2
112 blelr- 107 blelr-
108 sync
11300: lhzu r5,2(r4) 10900: lhzu r5,2(r4)
114 EIEIO_32
115 sthbrx r5,0,r3 110 sthbrx r5,0,r3
116 bdnz 00b 111 bdnz 00b
117 SYNC_64 112 sync
118 blr 113 blr
119 114
120_GLOBAL(_insl) 115_GLOBAL(_insl)
116 sync
121 cmpwi 0,r5,0 117 cmpwi 0,r5,0
122 mtctr r5 118 mtctr r5
123 subi r4,r4,4 119 subi r4,r4,4
@@ -126,7 +122,8 @@ _GLOBAL(_insl)
126 eieio 122 eieio
127 stwu r5,4(r4) 123 stwu r5,4(r4)
128 bdnz 00b 124 bdnz 00b
129 IN_SYNC 125 twi 0,r5,0
126 isync
130 blr 127 blr
131 128
132_GLOBAL(_outsl) 129_GLOBAL(_outsl)
@@ -134,17 +131,18 @@ _GLOBAL(_outsl)
134 mtctr r5 131 mtctr r5
135 subi r4,r4,4 132 subi r4,r4,4
136 blelr- 133 blelr-
134 sync
13700: lwzu r5,4(r4) 13500: lwzu r5,4(r4)
138 stwbrx r5,0,r3 136 stwbrx r5,0,r3
139 EIEIO_32
140 bdnz 00b 137 bdnz 00b
141 SYNC_64 138 sync
142 blr 139 blr
143 140
144#ifdef CONFIG_PPC32 141#ifdef CONFIG_PPC32
145_GLOBAL(__ide_mm_insw) 142_GLOBAL(__ide_mm_insw)
146#endif 143#endif
147_GLOBAL(_insw_ns) 144_GLOBAL(_insw_ns)
145 sync
148 cmpwi 0,r5,0 146 cmpwi 0,r5,0
149 mtctr r5 147 mtctr r5
150 subi r4,r4,2 148 subi r4,r4,2
@@ -153,7 +151,8 @@ _GLOBAL(_insw_ns)
153 eieio 151 eieio
154 sthu r5,2(r4) 152 sthu r5,2(r4)
155 bdnz 00b 153 bdnz 00b
156 IN_SYNC 154 twi 0,r5,0
155 isync
157 blr 156 blr
158 157
159#ifdef CONFIG_PPC32 158#ifdef CONFIG_PPC32
@@ -164,17 +163,18 @@ _GLOBAL(_outsw_ns)
164 mtctr r5 163 mtctr r5
165 subi r4,r4,2 164 subi r4,r4,2
166 blelr- 165 blelr-
166 sync
16700: lhzu r5,2(r4) 16700: lhzu r5,2(r4)
168 sth r5,0(r3) 168 sth r5,0(r3)
169 EIEIO_32
170 bdnz 00b 169 bdnz 00b
171 SYNC_64 170 sync
172 blr 171 blr
173 172
174#ifdef CONFIG_PPC32 173#ifdef CONFIG_PPC32
175_GLOBAL(__ide_mm_insl) 174_GLOBAL(__ide_mm_insl)
176#endif 175#endif
177_GLOBAL(_insl_ns) 176_GLOBAL(_insl_ns)
177 sync
178 cmpwi 0,r5,0 178 cmpwi 0,r5,0
179 mtctr r5 179 mtctr r5
180 subi r4,r4,4 180 subi r4,r4,4
@@ -183,7 +183,8 @@ _GLOBAL(_insl_ns)
183 eieio 183 eieio
184 stwu r5,4(r4) 184 stwu r5,4(r4)
185 bdnz 00b 185 bdnz 00b
186 IN_SYNC 186 twi 0,r5,0
187 isync
187 blr 188 blr
188 189
189#ifdef CONFIG_PPC32 190#ifdef CONFIG_PPC32
@@ -194,10 +195,10 @@ _GLOBAL(_outsl_ns)
194 mtctr r5 195 mtctr r5
195 subi r4,r4,4 196 subi r4,r4,4
196 blelr- 197 blelr-
198 sync
19700: lwzu r5,4(r4) 19900: lwzu r5,4(r4)
198 stw r5,0(r3) 200 stw r5,0(r3)
199 EIEIO_32
200 bdnz 00b 201 bdnz 00b
201 SYNC_64 202 sync
202 blr 203 blr
203 204