aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/kernel
diff options
context:
space:
mode:
authorKumar Gala <galak@kernel.crashing.org>2009-02-10 19:10:50 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-02-12 17:37:11 -0500
commitd66c82ea456853a71d88359b0c19a92ac1d393ff (patch)
tree13346439fc4f4186c096ae19387934c0d1dd3841 /arch/powerpc/kernel
parenta2404746f13b9df2cc6ee48010e921b9efdbba74 (diff)
powerpc/fsl-booke: Add new ISA 2.06 page sizes and MAS defines
The Power ISA 2.06 added power of two page sizes to the embedded MMU architecture. Its done it such a way to be code compatiable with the existing HW. Made the minor code changes to support both power of two and power of four page sizes. Also added some new MAS bits and macros that are defined as part of the 2.06 ISA. Renamed some things to use the 'Book-3e' concept to convey the new MMU that is based on the Freescale Book-E MMU programming model. Note, its still invalid to try and use a page size that isn't supported by cpu. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel')
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 64ecb1603a77..4ea6e1a7e4b9 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -173,7 +173,7 @@ skpinv: addi r6,r6,1 /* Increment */
173 173
174 /* grab and fixup the RPN */ 174 /* grab and fixup the RPN */
175 mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */ 175 mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
176 rlwinm r6,r6,25,27,30 176 rlwinm r6,r6,25,27,31
177 li r8,-1 177 li r8,-1
178 addi r6,r6,10 178 addi r6,r6,10
179 slw r6,r8,r6 /* convert to mask */ 179 slw r6,r8,r6 /* convert to mask */
@@ -199,7 +199,7 @@ skpinv: addi r6,r6,1 /* Increment */
199 xori r6,r4,1 /* Setup TMP mapping in the other Address space */ 199 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
200 slwi r6,r6,12 200 slwi r6,r6,12
201 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h 201 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
202 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_4K))@l 202 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
203 mtspr SPRN_MAS1,r6 203 mtspr SPRN_MAS1,r6
204 mfspr r6,SPRN_MAS2 204 mfspr r6,SPRN_MAS2
205 li r7,0 /* temp EPN = 0 */ 205 li r7,0 /* temp EPN = 0 */
@@ -257,10 +257,10 @@ skpinv: addi r6,r6,1 /* Increment */
257 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */ 257 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
258 mtspr SPRN_MAS0,r6 258 mtspr SPRN_MAS0,r6
259 lis r6,(MAS1_VALID|MAS1_IPROT)@h 259 lis r6,(MAS1_VALID|MAS1_IPROT)@h
260 ori r6,r6,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l 260 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
261 mtspr SPRN_MAS1,r6 261 mtspr SPRN_MAS1,r6
262 lis r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@h 262 lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
263 ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOKE_PAGESZ_64M, M_IF_SMP)@l 263 ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
264 mtspr SPRN_MAS2,r6 264 mtspr SPRN_MAS2,r6
265 mtspr SPRN_MAS3,r8 265 mtspr SPRN_MAS3,r8
266 tlbwe 266 tlbwe
@@ -315,7 +315,7 @@ skpinv: addi r6,r6,1 /* Increment */
315 mtspr SPRN_IVPR,r4 315 mtspr SPRN_IVPR,r4
316 316
317 /* Setup the defaults for TLB entries */ 317 /* Setup the defaults for TLB entries */
318 li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l 318 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
319#ifdef CONFIG_E200 319#ifdef CONFIG_E200
320 oris r2,r2,MAS4_TLBSELD(1)@h 320 oris r2,r2,MAS4_TLBSELD(1)@h
321#endif 321#endif
@@ -1116,7 +1116,7 @@ __secondary_start:
1116 mtspr SPRN_SPRG3,r4 1116 mtspr SPRN_SPRG3,r4
1117 1117
1118 /* Setup the defaults for TLB entries */ 1118 /* Setup the defaults for TLB entries */
1119 li r4,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l 1119 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1120 mtspr SPRN_MAS4,r4 1120 mtspr SPRN_MAS4,r4
1121 1121
1122 /* Jump to start_secondary */ 1122 /* Jump to start_secondary */