[PATCH] powerpc: Fix handling of fpscr on 64-bit

The recent merge of fpu.S broken the handling of fpscr for
ARCH=powerpc and CONFIG_PPC64=y.  FP registers could be corrupted,
leading to strange random application crashes.

The confusion arises, because the thread_struct has (and requires) a
64-bit area to save the fpscr, because we use load/store double
instructions to get it in to/out of the FPU.  However, only the low
32-bits are actually used, so we want to treat it as a 32-bit quantity
when manipulating its bits to avoid extra load/stores on 32-bit.  This
patch replaces the current definition with a structure of two 32-bit
quantities (pad and val), to clarify things as much as is possible.
The 'val' field is used when manipulating bits, the structure itself
is used when obtaining the address for loading/unloading the value
from the FPU.

While we're at it, consolidate the 4 (!) almost identical versions of
cvt_fd() and cvt_df() (arch/ppc/kernel/misc.S,
arch/ppc64/kernel/misc.S, arch/powerpc/kernel/misc_32.S,
arch/powerpc/kernel/misc_64.S) into a single version in fpu.S.  The
new version takes a pointer to thread_struct and applies the correct
offset itself, rather than a pointer to the fpscr field itself, again
to avoid confusion as to which is the correct field to use.

Finally, this patch makes ARCH=ppc64 also use the consolidated fpu.S
code, which it previously did not.

Built for G5 (ARCH=ppc64 and ARCH=powerpc), 32-bit powermac (ARCH=ppc
and ARCH=powerpc) and Walnut (ARCH=ppc, CONFIG_MATH_EMULATION=y).
Booted on G5 (ARCH=powerpc) and things which previously fell over no
longer do.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>

7 files changed, 33 insertions, 55 deletions

diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index a733347964a0..94cf917b7854 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -29,7 +29,6 @@ extra-$(CONFIG_44x)		:= head_44x.o
 extra-$(CONFIG_FSL_BOOKE)       := head_fsl_booke.o
 extra-$(CONFIG_8xx)             := head_8xx.o
 extra-$(CONFIG_PPC64)           += entry_64.o
-extra-$(CONFIG_PPC_FPU)         += fpu.o
 extra-y                         += vmlinux.lds
 
 obj-y                           += process.o init_task.o time.o \
@@ -49,7 +48,7 @@ else
 # stuff used from here for ARCH=ppc or ARCH=ppc64
 obj-$(CONFIG_PPC64)             += traps.o process.o init_task.o time.o
 
-fpux-$(CONFIG_PPC32)            += fpu.o
-extra-$(CONFIG_PPC_FPU)         += $(fpux-y)
 
 endif
+
+extra-$(CONFIG_PPC_FPU)         += fpu.o
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index 563d445ff584..51fd78da25b7 100644
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -48,7 +48,7 @@ _GLOBAL(load_up_fpu)
         addi    r4,r4,THREAD            /* want last_task_used_math->thread */
         SAVE_32FPRS(0, r4)
         mffs    fr0
-        stfd    fr0,THREAD_FPSCR-4(r4)
+        stfd    fr0,THREAD_FPSCR(r4)
         LDL     r5,PT_REGS(r4)
         tophys(r5,r5)
         LDL     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
@@ -71,7 +71,7 @@ _GLOBAL(load_up_fpu)
         or      r12,r12,r4
         std     r12,_MSR(r1)
 #endif
-        lfd     fr0,THREAD_FPSCR-4(r5)
+        lfd     fr0,THREAD_FPSCR(r5)
         mtfsf   0xff,fr0
         REST_32FPRS(0, r5)
 #ifndef CONFIG_SMP
@@ -104,7 +104,7 @@ _GLOBAL(giveup_fpu)
         CMPI    0,r5,0
         SAVE_32FPRS(0, r3)
         mffs    fr0
-        stfd    fr0,THREAD_FPSCR-4(r3)
+        stfd    fr0,THREAD_FPSCR(r3)
         beq     1f
         LDL     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
         li      r3,MSR_FP|MSR_FE0|MSR_FE1
@@ -117,3 +117,28 @@ _GLOBAL(giveup_fpu)
         STL     r5,OFF(last_task_used_math)(r4)
 #endif /* CONFIG_SMP */
         blr
+
+/*
+ * These are used in the alignment trap handler when emulating
+ * single-precision loads and stores.
+ * We restore and save the fpscr so the task gets the same result
+ * and exceptions as if the cpu had performed the load or store.
+ */
+
+_GLOBAL(cvt_fd)
+        lfd     0,THREAD_FPSCR(r5)      /* load up fpscr value */
+        mtfsf   0xff,0
+        lfs     0,0(r3)
+        stfd    0,0(r4)
+        mffs    0
+        stfd    0,THREAD_FPSCR(r5)      /* save new fpscr value */
+        blr
+
+_GLOBAL(cvt_df)
+        lfd     0,THREAD_FPSCR(r5)      /* load up fpscr value */
+        mtfsf   0xff,0
+        lfd     0,0(r3)
+        stfs    0,0(r4)
+        mffs    0
+        stfd    0,THREAD_FPSCR(r5)      /* save new fpscr value */
+        blr
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 303229b090b8..3bedb532aed9 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -993,33 +993,6 @@ _GLOBAL(_get_SP)
         blr
 
 /*
- * These are used in the alignment trap handler when emulating
- * single-precision loads and stores.
- * We restore and save the fpscr so the task gets the same result
- * and exceptions as if the cpu had performed the load or store.
- */
-
-#ifdef CONFIG_PPC_FPU
-_GLOBAL(cvt_fd)
-        lfd     0,-4(r5)        /* load up fpscr value */
-        mtfsf   0xff,0
-        lfs     0,0(r3)
-        stfd    0,0(r4)
-        mffs    0               /* save new fpscr value */
-        stfd    0,-4(r5)
-        blr
-
-_GLOBAL(cvt_df)
-        lfd     0,-4(r5)        /* load up fpscr value */
-        mtfsf   0xff,0
-        lfd     0,0(r3)
-        stfs    0,0(r4)
-        mffs    0               /* save new fpscr value */
-        stfd    0,-4(r5)
-        blr
-#endif
-
-/*
  * Create a kernel thread
  *   kernel_thread(fn, arg, flags)
  */
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index 4775bed42cac..b3e95ff0dba0 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -462,25 +462,6 @@ _GLOBAL(_outsl_ns)
         sync
         blr     
 
-
-_GLOBAL(cvt_fd)
-        lfd     0,0(r5)         /* load up fpscr value */
-        mtfsf   0xff,0
-        lfs     0,0(r3)
-        stfd    0,0(r4)
-        mffs    0               /* save new fpscr value */
-        stfd    0,0(r5)
-        blr
-
-_GLOBAL(cvt_df)
-        lfd     0,0(r5)         /* load up fpscr value */
-        mtfsf   0xff,0
-        lfd     0,0(r3)
-        stfs    0,0(r4)
-        mffs    0               /* save new fpscr value */
-        stfd    0,0(r5)
-        blr
-
 /*
  * identify_cpu and calls setup_cpu
  * In:  r3 = base of the cpu_specs array
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 047da1ae21fe..8f85dabe4df3 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -665,7 +665,7 @@ void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
 #endif
 #endif /* CONFIG_SMP */
         memset(current->thread.fpr, 0, sizeof(current->thread.fpr));
-        current->thread.fpscr = 0;
+        current->thread.fpscr.val = 0;
 #ifdef CONFIG_ALTIVEC
         memset(current->thread.vr, 0, sizeof(current->thread.vr));
         memset(&current->thread.vscr, 0, sizeof(current->thread.vscr));
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index 92452b2db26a..444c3e81884c 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -403,7 +403,7 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame,
                     ELF_NFPREG * sizeof(double)))
                 return 1;
 
-        current->thread.fpscr = 0;      /* turn off all fp exceptions */
+        current->thread.fpscr.val = 0;  /* turn off all fp exceptions */
 
 #ifdef CONFIG_ALTIVEC
         /* save altivec registers */
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index f87580382da4..5d638ecddbd0 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -549,7 +549,7 @@ static void parse_fpe(struct pt_regs *regs)
 
         flush_fp_to_thread(current);
 
-        fpscr = current->thread.fpscr;
+        fpscr = current->thread.fpscr.val;
 
         /* Invalid operation */
         if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))