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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-04-05 00:20:31 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2011-04-19 21:03:22 -0400
commita5d4f3ad3a28cf046836b9bfae61d532b8f77036 (patch)
tree6940ace9422e91459d819b385dacf9b2ab44bd50 /arch/powerpc/kernel
parent2dd60d79e0202628a47af9812a84d502cc63628c (diff)
powerpc: Base support for exceptions using HSRR0/1
Pass the register type to the prolog, also provides alternate "HV" version of hardware interrupt (0x500) and adjust LPES accordingly We tag those interrupts by setting bit 0x2 in the trap number Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel')
-rw-r--r--arch/powerpc/kernel/cpu_setup_power7.S3
-rw-r--r--arch/powerpc/kernel/exceptions-64s.S48
2 files changed, 39 insertions, 12 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_power7.S b/arch/powerpc/kernel/cpu_setup_power7.S
index f2b317817c4e..e801ef15d6d0 100644
--- a/arch/powerpc/kernel/cpu_setup_power7.S
+++ b/arch/powerpc/kernel/cpu_setup_power7.S
@@ -52,13 +52,14 @@ __init_hvmode_206:
52__init_LPCR: 52__init_LPCR:
53 /* Setup a sane LPCR: 53 /* Setup a sane LPCR:
54 * 54 *
55 * LPES = 0b11 (SRR0/1 used for 0x500) 55 * LPES = 0b01 (HSRR0/1 used for 0x500)
56 * PECE = 0b111 56 * PECE = 0b111
57 * 57 *
58 * Other bits untouched for now 58 * Other bits untouched for now
59 */ 59 */
60 mfspr r3,SPRN_LPCR 60 mfspr r3,SPRN_LPCR
61 ori r3,r3,(LPCR_LPES0|LPCR_LPES1) 61 ori r3,r3,(LPCR_LPES0|LPCR_LPES1)
62 xori r3,r3, LPCR_LPES0
62 ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2) 63 ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
63 mtspr SPRN_LPCR,r3 64 mtspr SPRN_LPCR,r3
64 isync 65 isync
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 6784bf7090f6..17f1d6670635 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -44,7 +44,7 @@ _machine_check_pSeries:
44 HMT_MEDIUM 44 HMT_MEDIUM
45 DO_KVM 0x200 45 DO_KVM 0x200
46 mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */ 46 mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */
47 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) 47 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common, EXC_STD)
48 48
49 . = 0x300 49 . = 0x300
50 .globl data_access_pSeries 50 .globl data_access_pSeries
@@ -71,9 +71,9 @@ BEGIN_FTR_SECTION
71 std r10,PACA_EXGEN+EX_R10(r13) 71 std r10,PACA_EXGEN+EX_R10(r13)
72 std r11,PACA_EXGEN+EX_R9(r13) 72 std r11,PACA_EXGEN+EX_R9(r13)
73 std r12,PACA_EXGEN+EX_R13(r13) 73 std r12,PACA_EXGEN+EX_R13(r13)
74 EXCEPTION_PROLOG_PSERIES_1(data_access_common) 74 EXCEPTION_PROLOG_PSERIES_1(data_access_common, EXC_STD)
75FTR_SECTION_ELSE 75FTR_SECTION_ELSE
76 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) 76 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD)
77ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB) 77ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
78 78
79 . = 0x380 79 . = 0x380
@@ -147,11 +147,24 @@ instruction_access_slb_pSeries:
147 bctr 147 bctr
148#endif 148#endif
149 149
150 MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt) 150 . = 0x500;
151 .globl hardware_interrupt_pSeries
152hardware_interrupt_pSeries:
153 BEGIN_FTR_SECTION
154 MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt, EXC_STD)
155 FTR_SECTION_ELSE
156 MASKABLE_EXCEPTION_PSERIES(0x502, hardware_interrupt, EXC_HV)
157 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_HVMODE_206)
158
151 STD_EXCEPTION_PSERIES(0x600, alignment) 159 STD_EXCEPTION_PSERIES(0x600, alignment)
152 STD_EXCEPTION_PSERIES(0x700, program_check) 160 STD_EXCEPTION_PSERIES(0x700, program_check)
153 STD_EXCEPTION_PSERIES(0x800, fp_unavailable) 161 STD_EXCEPTION_PSERIES(0x800, fp_unavailable)
154 MASKABLE_EXCEPTION_PSERIES(0x900, decrementer) 162
163 . = 0x900;
164 .globl decrementer_pSeries
165decrementer_pSeries:
166 MASKABLE_EXCEPTION_PSERIES(0x900, decrementer, EXC_STD)
167
155 STD_EXCEPTION_PSERIES(0xa00, trap_0a) 168 STD_EXCEPTION_PSERIES(0xa00, trap_0a)
156 STD_EXCEPTION_PSERIES(0xb00, trap_0b) 169 STD_EXCEPTION_PSERIES(0xb00, trap_0b)
157 170
@@ -207,15 +220,15 @@ vsx_unavailable_pSeries_1:
207 b vsx_unavailable_pSeries 220 b vsx_unavailable_pSeries
208 221
209#ifdef CONFIG_CBE_RAS 222#ifdef CONFIG_CBE_RAS
210 HSTD_EXCEPTION_PSERIES(0x1200, cbe_system_error) 223 HSTD_EXCEPTION_PSERIES(0x1202, cbe_system_error)
211#endif /* CONFIG_CBE_RAS */ 224#endif /* CONFIG_CBE_RAS */
212 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint) 225 STD_EXCEPTION_PSERIES(0x1300, instruction_breakpoint)
213#ifdef CONFIG_CBE_RAS 226#ifdef CONFIG_CBE_RAS
214 HSTD_EXCEPTION_PSERIES(0x1600, cbe_maintenance) 227 HSTD_EXCEPTION_PSERIES(0x1602, cbe_maintenance)
215#endif /* CONFIG_CBE_RAS */ 228#endif /* CONFIG_CBE_RAS */
216 STD_EXCEPTION_PSERIES(0x1700, altivec_assist) 229 STD_EXCEPTION_PSERIES(0x1700, altivec_assist)
217#ifdef CONFIG_CBE_RAS 230#ifdef CONFIG_CBE_RAS
218 HSTD_EXCEPTION_PSERIES(0x1800, cbe_thermal) 231 HSTD_EXCEPTION_PSERIES(0x1802, cbe_thermal)
219#endif /* CONFIG_CBE_RAS */ 232#endif /* CONFIG_CBE_RAS */
220 233
221 . = 0x3000 234 . = 0x3000
@@ -244,13 +257,26 @@ masked_interrupt:
244 rfid 257 rfid
245 b . 258 b .
246 259
260masked_Hinterrupt:
261 stb r10,PACAHARDIRQEN(r13)
262 mtcrf 0x80,r9
263 ld r9,PACA_EXGEN+EX_R9(r13)
264 mfspr r10,SPRN_HSRR1
265 rldicl r10,r10,48,1 /* clear MSR_EE */
266 rotldi r10,r10,16
267 mtspr SPRN_HSRR1,r10
268 ld r10,PACA_EXGEN+EX_R10(r13)
269 mfspr r13,SPRN_SPRG_HSCRATCH0
270 hrfid
271 b .
272
247 .align 7 273 .align 7
248do_stab_bolted_pSeries: 274do_stab_bolted_pSeries:
249 std r11,PACA_EXSLB+EX_R11(r13) 275 std r11,PACA_EXSLB+EX_R11(r13)
250 std r12,PACA_EXSLB+EX_R12(r13) 276 std r12,PACA_EXSLB+EX_R12(r13)
251 mfspr r10,SPRN_SPRG_SCRATCH0 277 mfspr r10,SPRN_SPRG_SCRATCH0
252 std r10,PACA_EXSLB+EX_R13(r13) 278 std r10,PACA_EXSLB+EX_R13(r13)
253 EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted) 279 EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted, EXC_STD)
254 280
255#ifdef CONFIG_PPC_PSERIES 281#ifdef CONFIG_PPC_PSERIES
256/* 282/*
@@ -261,14 +287,14 @@ do_stab_bolted_pSeries:
261system_reset_fwnmi: 287system_reset_fwnmi:
262 HMT_MEDIUM 288 HMT_MEDIUM
263 mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */ 289 mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */
264 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common) 290 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD)
265 291
266 .globl machine_check_fwnmi 292 .globl machine_check_fwnmi
267 .align 7 293 .align 7
268machine_check_fwnmi: 294machine_check_fwnmi:
269 HMT_MEDIUM 295 HMT_MEDIUM
270 mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */ 296 mtspr SPRN_SPRG_SCRATCH0,r13 /* save r13 */
271 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) 297 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common, EXC_STD)
272 298
273#endif /* CONFIG_PPC_PSERIES */ 299#endif /* CONFIG_PPC_PSERIES */
274 300