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authorPaul Mackerras <paulus@samba.org>2009-06-17 07:51:13 -0400
committerIngo Molnar <mingo@elte.hu>2009-06-18 05:11:45 -0400
commit448d64f8f4c147db466c549550767cc515a4d34c (patch)
tree9c33191273219d8e4d77e3ea78304691e4fb4b56 /arch/powerpc/kernel
parent105988c015943e77092a6568bc5fb7e386df6ccd (diff)
perf_counter: powerpc: Use unsigned long for register and constraint values
This changes the powerpc perf_counter back-end to use unsigned long types for hardware register values and for the value/mask pairs used in checking whether a given set of events fit within the hardware constraints. This is in preparation for adding support for the PMU on some 32-bit powerpc processors. On 32-bit processors the hardware registers are only 32 bits wide, and the PMU structure is generally simpler, so 32 bits should be ample for expressing the hardware constraints. On 64-bit processors, unsigned long is 64 bits wide, so using unsigned long vs. u64 (unsigned long long) makes no actual difference. This makes some other very minor changes: adjusting whitespace to line things up in initialized structures, and simplifying some code in hw_perf_disable(). Signed-off-by: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: linuxppc-dev@ozlabs.org Cc: benh@kernel.crashing.org LKML-Reference: <19000.55473.26174.331511@cargo.ozlabs.ibm.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/powerpc/kernel')
-rw-r--r--arch/powerpc/kernel/perf_counter.c20
-rw-r--r--arch/powerpc/kernel/power4-pmu.c74
-rw-r--r--arch/powerpc/kernel/power5+-pmu.c79
-rw-r--r--arch/powerpc/kernel/power5-pmu.c83
-rw-r--r--arch/powerpc/kernel/power6-pmu.c57
-rw-r--r--arch/powerpc/kernel/power7-pmu.c46
-rw-r--r--arch/powerpc/kernel/ppc970-pmu.c47
7 files changed, 211 insertions, 195 deletions
diff --git a/arch/powerpc/kernel/perf_counter.c b/arch/powerpc/kernel/perf_counter.c
index e6dc1850191c..9300638b8c26 100644
--- a/arch/powerpc/kernel/perf_counter.c
+++ b/arch/powerpc/kernel/perf_counter.c
@@ -29,7 +29,7 @@ struct cpu_hw_counters {
29 struct perf_counter *counter[MAX_HWCOUNTERS]; 29 struct perf_counter *counter[MAX_HWCOUNTERS];
30 u64 events[MAX_HWCOUNTERS]; 30 u64 events[MAX_HWCOUNTERS];
31 unsigned int flags[MAX_HWCOUNTERS]; 31 unsigned int flags[MAX_HWCOUNTERS];
32 u64 mmcr[3]; 32 unsigned long mmcr[3];
33 struct perf_counter *limited_counter[MAX_LIMITED_HWCOUNTERS]; 33 struct perf_counter *limited_counter[MAX_LIMITED_HWCOUNTERS];
34 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; 34 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
35}; 35};
@@ -135,15 +135,15 @@ static void write_pmc(int idx, unsigned long val)
135static int power_check_constraints(u64 event[], unsigned int cflags[], 135static int power_check_constraints(u64 event[], unsigned int cflags[],
136 int n_ev) 136 int n_ev)
137{ 137{
138 u64 mask, value, nv; 138 unsigned long mask, value, nv;
139 u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; 139 u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
140 u64 amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; 140 unsigned long amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
141 u64 avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; 141 unsigned long avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
142 u64 smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS]; 142 unsigned long smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS];
143 int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS]; 143 int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS];
144 int i, j; 144 int i, j;
145 u64 addf = ppmu->add_fields; 145 unsigned long addf = ppmu->add_fields;
146 u64 tadd = ppmu->test_adder; 146 unsigned long tadd = ppmu->test_adder;
147 147
148 if (n_ev > ppmu->n_counter) 148 if (n_ev > ppmu->n_counter)
149 return -1; 149 return -1;
@@ -403,14 +403,12 @@ static void write_mmcr0(struct cpu_hw_counters *cpuhw, unsigned long mmcr0)
403void hw_perf_disable(void) 403void hw_perf_disable(void)
404{ 404{
405 struct cpu_hw_counters *cpuhw; 405 struct cpu_hw_counters *cpuhw;
406 unsigned long ret;
407 unsigned long flags; 406 unsigned long flags;
408 407
409 local_irq_save(flags); 408 local_irq_save(flags);
410 cpuhw = &__get_cpu_var(cpu_hw_counters); 409 cpuhw = &__get_cpu_var(cpu_hw_counters);
411 410
412 ret = cpuhw->disabled; 411 if (!cpuhw->disabled) {
413 if (!ret) {
414 cpuhw->disabled = 1; 412 cpuhw->disabled = 1;
415 cpuhw->n_added = 0; 413 cpuhw->n_added = 0;
416 414
@@ -1013,9 +1011,9 @@ static void record_and_restart(struct perf_counter *counter, long val,
1013 struct pt_regs *regs, int nmi) 1011 struct pt_regs *regs, int nmi)
1014{ 1012{
1015 u64 period = counter->hw.sample_period; 1013 u64 period = counter->hw.sample_period;
1014 unsigned long mmcra, sdsync;
1016 s64 prev, delta, left; 1015 s64 prev, delta, left;
1017 int record = 0; 1016 int record = 0;
1018 u64 mmcra, sdsync;
1019 1017
1020 /* we don't have to worry about interrupts here */ 1018 /* we don't have to worry about interrupts here */
1021 prev = atomic64_read(&counter->hw.prev_count); 1019 prev = atomic64_read(&counter->hw.prev_count);
diff --git a/arch/powerpc/kernel/power4-pmu.c b/arch/powerpc/kernel/power4-pmu.c
index 07bd308a5fa7..81a1708f83b2 100644
--- a/arch/powerpc/kernel/power4-pmu.c
+++ b/arch/powerpc/kernel/power4-pmu.c
@@ -179,22 +179,22 @@ static short mmcr1_adder_bits[8] = {
179 */ 179 */
180 180
181static struct unitinfo { 181static struct unitinfo {
182 u64 value, mask; 182 unsigned long value, mask;
183 int unit; 183 int unit;
184 int lowerbit; 184 int lowerbit;
185} p4_unitinfo[16] = { 185} p4_unitinfo[16] = {
186 [PM_FPU] = { 0x44000000000000ull, 0x88000000000000ull, PM_FPU, 0 }, 186 [PM_FPU] = { 0x44000000000000ul, 0x88000000000000ul, PM_FPU, 0 },
187 [PM_ISU1] = { 0x20080000000000ull, 0x88000000000000ull, PM_ISU1, 0 }, 187 [PM_ISU1] = { 0x20080000000000ul, 0x88000000000000ul, PM_ISU1, 0 },
188 [PM_ISU1_ALT] = 188 [PM_ISU1_ALT] =
189 { 0x20080000000000ull, 0x88000000000000ull, PM_ISU1, 0 }, 189 { 0x20080000000000ul, 0x88000000000000ul, PM_ISU1, 0 },
190 [PM_IFU] = { 0x02200000000000ull, 0x08820000000000ull, PM_IFU, 41 }, 190 [PM_IFU] = { 0x02200000000000ul, 0x08820000000000ul, PM_IFU, 41 },
191 [PM_IFU_ALT] = 191 [PM_IFU_ALT] =
192 { 0x02200000000000ull, 0x08820000000000ull, PM_IFU, 41 }, 192 { 0x02200000000000ul, 0x08820000000000ul, PM_IFU, 41 },
193 [PM_IDU0] = { 0x10100000000000ull, 0x80840000000000ull, PM_IDU0, 1 }, 193 [PM_IDU0] = { 0x10100000000000ul, 0x80840000000000ul, PM_IDU0, 1 },
194 [PM_ISU2] = { 0x10140000000000ull, 0x80840000000000ull, PM_ISU2, 0 }, 194 [PM_ISU2] = { 0x10140000000000ul, 0x80840000000000ul, PM_ISU2, 0 },
195 [PM_LSU0] = { 0x01400000000000ull, 0x08800000000000ull, PM_LSU0, 0 }, 195 [PM_LSU0] = { 0x01400000000000ul, 0x08800000000000ul, PM_LSU0, 0 },
196 [PM_LSU1] = { 0x00000000000000ull, 0x00010000000000ull, PM_LSU1, 40 }, 196 [PM_LSU1] = { 0x00000000000000ul, 0x00010000000000ul, PM_LSU1, 40 },
197 [PM_GPS] = { 0x00000000000000ull, 0x00000000000000ull, PM_GPS, 0 } 197 [PM_GPS] = { 0x00000000000000ul, 0x00000000000000ul, PM_GPS, 0 }
198}; 198};
199 199
200static unsigned char direct_marked_event[8] = { 200static unsigned char direct_marked_event[8] = {
@@ -249,10 +249,11 @@ static int p4_marked_instr_event(u64 event)
249 return (mask >> (byte * 8 + bit)) & 1; 249 return (mask >> (byte * 8 + bit)) & 1;
250} 250}
251 251
252static int p4_get_constraint(u64 event, u64 *maskp, u64 *valp) 252static int p4_get_constraint(u64 event, unsigned long *maskp,
253 unsigned long *valp)
253{ 254{
254 int pmc, byte, unit, lower, sh; 255 int pmc, byte, unit, lower, sh;
255 u64 mask = 0, value = 0; 256 unsigned long mask = 0, value = 0;
256 int grp = -1; 257 int grp = -1;
257 258
258 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 259 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
@@ -282,14 +283,14 @@ static int p4_get_constraint(u64 event, u64 *maskp, u64 *valp)
282 value |= p4_unitinfo[unit].value; 283 value |= p4_unitinfo[unit].value;
283 sh = p4_unitinfo[unit].lowerbit; 284 sh = p4_unitinfo[unit].lowerbit;
284 if (sh > 1) 285 if (sh > 1)
285 value |= (u64)lower << sh; 286 value |= (unsigned long)lower << sh;
286 else if (lower != sh) 287 else if (lower != sh)
287 return -1; 288 return -1;
288 unit = p4_unitinfo[unit].unit; 289 unit = p4_unitinfo[unit].unit;
289 290
290 /* Set byte lane select field */ 291 /* Set byte lane select field */
291 mask |= 0xfULL << (28 - 4 * byte); 292 mask |= 0xfULL << (28 - 4 * byte);
292 value |= (u64)unit << (28 - 4 * byte); 293 value |= (unsigned long)unit << (28 - 4 * byte);
293 } 294 }
294 if (grp == 0) { 295 if (grp == 0) {
295 /* increment PMC1/2/5/6 field */ 296 /* increment PMC1/2/5/6 field */
@@ -353,9 +354,9 @@ static int p4_get_alternatives(u64 event, unsigned int flags, u64 alt[])
353} 354}
354 355
355static int p4_compute_mmcr(u64 event[], int n_ev, 356static int p4_compute_mmcr(u64 event[], int n_ev,
356 unsigned int hwc[], u64 mmcr[]) 357 unsigned int hwc[], unsigned long mmcr[])
357{ 358{
358 u64 mmcr0 = 0, mmcr1 = 0, mmcra = 0; 359 unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0;
359 unsigned int pmc, unit, byte, psel, lower; 360 unsigned int pmc, unit, byte, psel, lower;
360 unsigned int ttm, grp; 361 unsigned int ttm, grp;
361 unsigned int pmc_inuse = 0; 362 unsigned int pmc_inuse = 0;
@@ -429,9 +430,11 @@ static int p4_compute_mmcr(u64 event[], int n_ev,
429 return -1; 430 return -1;
430 431
431 /* Set TTMxSEL fields. Note, units 1-3 => TTM0SEL codes 0-2 */ 432 /* Set TTMxSEL fields. Note, units 1-3 => TTM0SEL codes 0-2 */
432 mmcr1 |= (u64)(unituse[3] * 2 + unituse[2]) << MMCR1_TTM0SEL_SH; 433 mmcr1 |= (unsigned long)(unituse[3] * 2 + unituse[2])
433 mmcr1 |= (u64)(unituse[7] * 3 + unituse[6] * 2) << MMCR1_TTM1SEL_SH; 434 << MMCR1_TTM0SEL_SH;
434 mmcr1 |= (u64)unituse[9] << MMCR1_TTM2SEL_SH; 435 mmcr1 |= (unsigned long)(unituse[7] * 3 + unituse[6] * 2)
436 << MMCR1_TTM1SEL_SH;
437 mmcr1 |= (unsigned long)unituse[9] << MMCR1_TTM2SEL_SH;
435 438
436 /* Set TTCxSEL fields. */ 439 /* Set TTCxSEL fields. */
437 if (unitlower & 0xe) 440 if (unitlower & 0xe)
@@ -456,7 +459,8 @@ static int p4_compute_mmcr(u64 event[], int n_ev,
456 ttm = unit - 1; /* 2->1, 3->2 */ 459 ttm = unit - 1; /* 2->1, 3->2 */
457 else 460 else
458 ttm = unit >> 2; 461 ttm = unit >> 2;
459 mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2*byte); 462 mmcr1 |= (unsigned long)ttm
463 << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
460 } 464 }
461 } 465 }
462 466
@@ -519,7 +523,7 @@ static int p4_compute_mmcr(u64 event[], int n_ev,
519 return 0; 523 return 0;
520} 524}
521 525
522static void p4_disable_pmc(unsigned int pmc, u64 mmcr[]) 526static void p4_disable_pmc(unsigned int pmc, unsigned long mmcr[])
523{ 527{
524 /* 528 /*
525 * Setting the PMCxSEL field to 0 disables PMC x. 529 * Setting the PMCxSEL field to 0 disables PMC x.
@@ -584,15 +588,15 @@ static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
584}; 588};
585 589
586struct power_pmu power4_pmu = { 590struct power_pmu power4_pmu = {
587 .n_counter = 8, 591 .n_counter = 8,
588 .max_alternatives = 5, 592 .max_alternatives = 5,
589 .add_fields = 0x0000001100005555ull, 593 .add_fields = 0x0000001100005555ul,
590 .test_adder = 0x0011083300000000ull, 594 .test_adder = 0x0011083300000000ul,
591 .compute_mmcr = p4_compute_mmcr, 595 .compute_mmcr = p4_compute_mmcr,
592 .get_constraint = p4_get_constraint, 596 .get_constraint = p4_get_constraint,
593 .get_alternatives = p4_get_alternatives, 597 .get_alternatives = p4_get_alternatives,
594 .disable_pmc = p4_disable_pmc, 598 .disable_pmc = p4_disable_pmc,
595 .n_generic = ARRAY_SIZE(p4_generic_events), 599 .n_generic = ARRAY_SIZE(p4_generic_events),
596 .generic_events = p4_generic_events, 600 .generic_events = p4_generic_events,
597 .cache_events = &power4_cache_events, 601 .cache_events = &power4_cache_events,
598}; 602};
diff --git a/arch/powerpc/kernel/power5+-pmu.c b/arch/powerpc/kernel/power5+-pmu.c
index 41e5d2d958d4..aef144d503b0 100644
--- a/arch/powerpc/kernel/power5+-pmu.c
+++ b/arch/powerpc/kernel/power5+-pmu.c
@@ -126,20 +126,21 @@ static const int grsel_shift[8] = {
126}; 126};
127 127
128/* Masks and values for using events from the various units */ 128/* Masks and values for using events from the various units */
129static u64 unit_cons[PM_LASTUNIT+1][2] = { 129static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
130 [PM_FPU] = { 0x3200000000ull, 0x0100000000ull }, 130 [PM_FPU] = { 0x3200000000ul, 0x0100000000ul },
131 [PM_ISU0] = { 0x0200000000ull, 0x0080000000ull }, 131 [PM_ISU0] = { 0x0200000000ul, 0x0080000000ul },
132 [PM_ISU1] = { 0x3200000000ull, 0x3100000000ull }, 132 [PM_ISU1] = { 0x3200000000ul, 0x3100000000ul },
133 [PM_IFU] = { 0x3200000000ull, 0x2100000000ull }, 133 [PM_IFU] = { 0x3200000000ul, 0x2100000000ul },
134 [PM_IDU] = { 0x0e00000000ull, 0x0040000000ull }, 134 [PM_IDU] = { 0x0e00000000ul, 0x0040000000ul },
135 [PM_GRS] = { 0x0e00000000ull, 0x0c40000000ull }, 135 [PM_GRS] = { 0x0e00000000ul, 0x0c40000000ul },
136}; 136};
137 137
138static int power5p_get_constraint(u64 event, u64 *maskp, u64 *valp) 138static int power5p_get_constraint(u64 event, unsigned long *maskp,
139 unsigned long *valp)
139{ 140{
140 int pmc, byte, unit, sh; 141 int pmc, byte, unit, sh;
141 int bit, fmask; 142 int bit, fmask;
142 u64 mask = 0, value = 0; 143 unsigned long mask = 0, value = 0;
143 144
144 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 145 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
145 if (pmc) { 146 if (pmc) {
@@ -171,17 +172,18 @@ static int power5p_get_constraint(u64 event, u64 *maskp, u64 *valp)
171 bit = event & 7; 172 bit = event & 7;
172 fmask = (bit == 6)? 7: 3; 173 fmask = (bit == 6)? 7: 3;
173 sh = grsel_shift[bit]; 174 sh = grsel_shift[bit];
174 mask |= (u64)fmask << sh; 175 mask |= (unsigned long)fmask << sh;
175 value |= (u64)((event >> PM_GRS_SH) & fmask) << sh; 176 value |= (unsigned long)((event >> PM_GRS_SH) & fmask)
177 << sh;
176 } 178 }
177 /* Set byte lane select field */ 179 /* Set byte lane select field */
178 mask |= 0xfULL << (24 - 4 * byte); 180 mask |= 0xfUL << (24 - 4 * byte);
179 value |= (u64)unit << (24 - 4 * byte); 181 value |= (unsigned long)unit << (24 - 4 * byte);
180 } 182 }
181 if (pmc < 5) { 183 if (pmc < 5) {
182 /* need a counter from PMC1-4 set */ 184 /* need a counter from PMC1-4 set */
183 mask |= 0x8000000000000ull; 185 mask |= 0x8000000000000ul;
184 value |= 0x1000000000000ull; 186 value |= 0x1000000000000ul;
185 } 187 }
186 *maskp = mask; 188 *maskp = mask;
187 *valp = value; 189 *valp = value;
@@ -452,10 +454,10 @@ static int power5p_marked_instr_event(u64 event)
452} 454}
453 455
454static int power5p_compute_mmcr(u64 event[], int n_ev, 456static int power5p_compute_mmcr(u64 event[], int n_ev,
455 unsigned int hwc[], u64 mmcr[]) 457 unsigned int hwc[], unsigned long mmcr[])
456{ 458{
457 u64 mmcr1 = 0; 459 unsigned long mmcr1 = 0;
458 u64 mmcra = 0; 460 unsigned long mmcra = 0;
459 unsigned int pmc, unit, byte, psel; 461 unsigned int pmc, unit, byte, psel;
460 unsigned int ttm; 462 unsigned int ttm;
461 int i, isbus, bit, grsel; 463 int i, isbus, bit, grsel;
@@ -517,7 +519,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
517 continue; 519 continue;
518 if (ttmuse++) 520 if (ttmuse++)
519 return -1; 521 return -1;
520 mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH; 522 mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH;
521 } 523 }
522 ttmuse = 0; 524 ttmuse = 0;
523 for (; i <= PM_GRS; ++i) { 525 for (; i <= PM_GRS; ++i) {
@@ -525,7 +527,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
525 continue; 527 continue;
526 if (ttmuse++) 528 if (ttmuse++)
527 return -1; 529 return -1;
528 mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH; 530 mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH;
529 } 531 }
530 if (ttmuse > 1) 532 if (ttmuse > 1)
531 return -1; 533 return -1;
@@ -540,10 +542,11 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
540 unit = PM_ISU0_ALT; 542 unit = PM_ISU0_ALT;
541 } else if (unit == PM_LSU1 + 1) { 543 } else if (unit == PM_LSU1 + 1) {
542 /* select lower word of LSU1 for this byte */ 544 /* select lower word of LSU1 for this byte */
543 mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte); 545 mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte);
544 } 546 }
545 ttm = unit >> 2; 547 ttm = unit >> 2;
546 mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); 548 mmcr1 |= (unsigned long)ttm
549 << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
547 } 550 }
548 551
549 /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */ 552 /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
@@ -568,7 +571,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
568 if (isbus && (byte & 2) && 571 if (isbus && (byte & 2) &&
569 (psel == 8 || psel == 0x10 || psel == 0x28)) 572 (psel == 8 || psel == 0x10 || psel == 0x28))
570 /* add events on higher-numbered bus */ 573 /* add events on higher-numbered bus */
571 mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc); 574 mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
572 } else { 575 } else {
573 /* Instructions or run cycles on PMC5/6 */ 576 /* Instructions or run cycles on PMC5/6 */
574 --pmc; 577 --pmc;
@@ -576,7 +579,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
576 if (isbus && unit == PM_GRS) { 579 if (isbus && unit == PM_GRS) {
577 bit = psel & 7; 580 bit = psel & 7;
578 grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK; 581 grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
579 mmcr1 |= (u64)grsel << grsel_shift[bit]; 582 mmcr1 |= (unsigned long)grsel << grsel_shift[bit];
580 } 583 }
581 if (power5p_marked_instr_event(event[i])) 584 if (power5p_marked_instr_event(event[i]))
582 mmcra |= MMCRA_SAMPLE_ENABLE; 585 mmcra |= MMCRA_SAMPLE_ENABLE;
@@ -599,7 +602,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
599 return 0; 602 return 0;
600} 603}
601 604
602static void power5p_disable_pmc(unsigned int pmc, u64 mmcr[]) 605static void power5p_disable_pmc(unsigned int pmc, unsigned long mmcr[])
603{ 606{
604 if (pmc <= 3) 607 if (pmc <= 3)
605 mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc)); 608 mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
@@ -655,17 +658,17 @@ static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
655}; 658};
656 659
657struct power_pmu power5p_pmu = { 660struct power_pmu power5p_pmu = {
658 .n_counter = 6, 661 .n_counter = 6,
659 .max_alternatives = MAX_ALT, 662 .max_alternatives = MAX_ALT,
660 .add_fields = 0x7000000000055ull, 663 .add_fields = 0x7000000000055ul,
661 .test_adder = 0x3000040000000ull, 664 .test_adder = 0x3000040000000ul,
662 .compute_mmcr = power5p_compute_mmcr, 665 .compute_mmcr = power5p_compute_mmcr,
663 .get_constraint = power5p_get_constraint, 666 .get_constraint = power5p_get_constraint,
664 .get_alternatives = power5p_get_alternatives, 667 .get_alternatives = power5p_get_alternatives,
665 .disable_pmc = power5p_disable_pmc, 668 .disable_pmc = power5p_disable_pmc,
666 .limited_pmc_event = power5p_limited_pmc_event, 669 .limited_pmc_event = power5p_limited_pmc_event,
667 .flags = PPMU_LIMITED_PMC5_6, 670 .flags = PPMU_LIMITED_PMC5_6,
668 .n_generic = ARRAY_SIZE(power5p_generic_events), 671 .n_generic = ARRAY_SIZE(power5p_generic_events),
669 .generic_events = power5p_generic_events, 672 .generic_events = power5p_generic_events,
670 .cache_events = &power5p_cache_events, 673 .cache_events = &power5p_cache_events,
671}; 674};
diff --git a/arch/powerpc/kernel/power5-pmu.c b/arch/powerpc/kernel/power5-pmu.c
index 05600b66221a..8694c73bfb52 100644
--- a/arch/powerpc/kernel/power5-pmu.c
+++ b/arch/powerpc/kernel/power5-pmu.c
@@ -130,20 +130,21 @@ static const int grsel_shift[8] = {
130}; 130};
131 131
132/* Masks and values for using events from the various units */ 132/* Masks and values for using events from the various units */
133static u64 unit_cons[PM_LASTUNIT+1][2] = { 133static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
134 [PM_FPU] = { 0xc0002000000000ull, 0x00001000000000ull }, 134 [PM_FPU] = { 0xc0002000000000ul, 0x00001000000000ul },
135 [PM_ISU0] = { 0x00002000000000ull, 0x00000800000000ull }, 135 [PM_ISU0] = { 0x00002000000000ul, 0x00000800000000ul },
136 [PM_ISU1] = { 0xc0002000000000ull, 0xc0001000000000ull }, 136 [PM_ISU1] = { 0xc0002000000000ul, 0xc0001000000000ul },
137 [PM_IFU] = { 0xc0002000000000ull, 0x80001000000000ull }, 137 [PM_IFU] = { 0xc0002000000000ul, 0x80001000000000ul },
138 [PM_IDU] = { 0x30002000000000ull, 0x00000400000000ull }, 138 [PM_IDU] = { 0x30002000000000ul, 0x00000400000000ul },
139 [PM_GRS] = { 0x30002000000000ull, 0x30000400000000ull }, 139 [PM_GRS] = { 0x30002000000000ul, 0x30000400000000ul },
140}; 140};
141 141
142static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp) 142static int power5_get_constraint(u64 event, unsigned long *maskp,
143 unsigned long *valp)
143{ 144{
144 int pmc, byte, unit, sh; 145 int pmc, byte, unit, sh;
145 int bit, fmask; 146 int bit, fmask;
146 u64 mask = 0, value = 0; 147 unsigned long mask = 0, value = 0;
147 int grp = -1; 148 int grp = -1;
148 149
149 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 150 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
@@ -178,8 +179,9 @@ static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp)
178 bit = event & 7; 179 bit = event & 7;
179 fmask = (bit == 6)? 7: 3; 180 fmask = (bit == 6)? 7: 3;
180 sh = grsel_shift[bit]; 181 sh = grsel_shift[bit];
181 mask |= (u64)fmask << sh; 182 mask |= (unsigned long)fmask << sh;
182 value |= (u64)((event >> PM_GRS_SH) & fmask) << sh; 183 value |= (unsigned long)((event >> PM_GRS_SH) & fmask)
184 << sh;
183 } 185 }
184 /* 186 /*
185 * Bus events on bytes 0 and 2 can be counted 187 * Bus events on bytes 0 and 2 can be counted
@@ -188,22 +190,22 @@ static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp)
188 if (!pmc) 190 if (!pmc)
189 grp = byte & 1; 191 grp = byte & 1;
190 /* Set byte lane select field */ 192 /* Set byte lane select field */
191 mask |= 0xfULL << (24 - 4 * byte); 193 mask |= 0xfUL << (24 - 4 * byte);
192 value |= (u64)unit << (24 - 4 * byte); 194 value |= (unsigned long)unit << (24 - 4 * byte);
193 } 195 }
194 if (grp == 0) { 196 if (grp == 0) {
195 /* increment PMC1/2 field */ 197 /* increment PMC1/2 field */
196 mask |= 0x200000000ull; 198 mask |= 0x200000000ul;
197 value |= 0x080000000ull; 199 value |= 0x080000000ul;
198 } else if (grp == 1) { 200 } else if (grp == 1) {
199 /* increment PMC3/4 field */ 201 /* increment PMC3/4 field */
200 mask |= 0x40000000ull; 202 mask |= 0x40000000ul;
201 value |= 0x10000000ull; 203 value |= 0x10000000ul;
202 } 204 }
203 if (pmc < 5) { 205 if (pmc < 5) {
204 /* need a counter from PMC1-4 set */ 206 /* need a counter from PMC1-4 set */
205 mask |= 0x8000000000000ull; 207 mask |= 0x8000000000000ul;
206 value |= 0x1000000000000ull; 208 value |= 0x1000000000000ul;
207 } 209 }
208 *maskp = mask; 210 *maskp = mask;
209 *valp = value; 211 *valp = value;
@@ -383,10 +385,10 @@ static int power5_marked_instr_event(u64 event)
383} 385}
384 386
385static int power5_compute_mmcr(u64 event[], int n_ev, 387static int power5_compute_mmcr(u64 event[], int n_ev,
386 unsigned int hwc[], u64 mmcr[]) 388 unsigned int hwc[], unsigned long mmcr[])
387{ 389{
388 u64 mmcr1 = 0; 390 unsigned long mmcr1 = 0;
389 u64 mmcra = 0; 391 unsigned long mmcra = 0;
390 unsigned int pmc, unit, byte, psel; 392 unsigned int pmc, unit, byte, psel;
391 unsigned int ttm, grp; 393 unsigned int ttm, grp;
392 int i, isbus, bit, grsel; 394 int i, isbus, bit, grsel;
@@ -457,7 +459,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
457 continue; 459 continue;
458 if (ttmuse++) 460 if (ttmuse++)
459 return -1; 461 return -1;
460 mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH; 462 mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH;
461 } 463 }
462 ttmuse = 0; 464 ttmuse = 0;
463 for (; i <= PM_GRS; ++i) { 465 for (; i <= PM_GRS; ++i) {
@@ -465,7 +467,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
465 continue; 467 continue;
466 if (ttmuse++) 468 if (ttmuse++)
467 return -1; 469 return -1;
468 mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH; 470 mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH;
469 } 471 }
470 if (ttmuse > 1) 472 if (ttmuse > 1)
471 return -1; 473 return -1;
@@ -480,10 +482,11 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
480 unit = PM_ISU0_ALT; 482 unit = PM_ISU0_ALT;
481 } else if (unit == PM_LSU1 + 1) { 483 } else if (unit == PM_LSU1 + 1) {
482 /* select lower word of LSU1 for this byte */ 484 /* select lower word of LSU1 for this byte */
483 mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte); 485 mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte);
484 } 486 }
485 ttm = unit >> 2; 487 ttm = unit >> 2;
486 mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); 488 mmcr1 |= (unsigned long)ttm
489 << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
487 } 490 }
488 491
489 /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */ 492 /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
@@ -513,7 +516,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
513 --pmc; 516 --pmc;
514 if ((psel == 8 || psel == 0x10) && isbus && (byte & 2)) 517 if ((psel == 8 || psel == 0x10) && isbus && (byte & 2))
515 /* add events on higher-numbered bus */ 518 /* add events on higher-numbered bus */
516 mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc); 519 mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
517 } else { 520 } else {
518 /* Instructions or run cycles on PMC5/6 */ 521 /* Instructions or run cycles on PMC5/6 */
519 --pmc; 522 --pmc;
@@ -521,7 +524,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
521 if (isbus && unit == PM_GRS) { 524 if (isbus && unit == PM_GRS) {
522 bit = psel & 7; 525 bit = psel & 7;
523 grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK; 526 grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
524 mmcr1 |= (u64)grsel << grsel_shift[bit]; 527 mmcr1 |= (unsigned long)grsel << grsel_shift[bit];
525 } 528 }
526 if (power5_marked_instr_event(event[i])) 529 if (power5_marked_instr_event(event[i]))
527 mmcra |= MMCRA_SAMPLE_ENABLE; 530 mmcra |= MMCRA_SAMPLE_ENABLE;
@@ -541,7 +544,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
541 return 0; 544 return 0;
542} 545}
543 546
544static void power5_disable_pmc(unsigned int pmc, u64 mmcr[]) 547static void power5_disable_pmc(unsigned int pmc, unsigned long mmcr[])
545{ 548{
546 if (pmc <= 3) 549 if (pmc <= 3)
547 mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc)); 550 mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
@@ -597,15 +600,15 @@ static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
597}; 600};
598 601
599struct power_pmu power5_pmu = { 602struct power_pmu power5_pmu = {
600 .n_counter = 6, 603 .n_counter = 6,
601 .max_alternatives = MAX_ALT, 604 .max_alternatives = MAX_ALT,
602 .add_fields = 0x7000090000555ull, 605 .add_fields = 0x7000090000555ul,
603 .test_adder = 0x3000490000000ull, 606 .test_adder = 0x3000490000000ul,
604 .compute_mmcr = power5_compute_mmcr, 607 .compute_mmcr = power5_compute_mmcr,
605 .get_constraint = power5_get_constraint, 608 .get_constraint = power5_get_constraint,
606 .get_alternatives = power5_get_alternatives, 609 .get_alternatives = power5_get_alternatives,
607 .disable_pmc = power5_disable_pmc, 610 .disable_pmc = power5_disable_pmc,
608 .n_generic = ARRAY_SIZE(power5_generic_events), 611 .n_generic = ARRAY_SIZE(power5_generic_events),
609 .generic_events = power5_generic_events, 612 .generic_events = power5_generic_events,
610 .cache_events = &power5_cache_events, 613 .cache_events = &power5_cache_events,
611}; 614};
diff --git a/arch/powerpc/kernel/power6-pmu.c b/arch/powerpc/kernel/power6-pmu.c
index 46f74bebcfd9..8898622ac28c 100644
--- a/arch/powerpc/kernel/power6-pmu.c
+++ b/arch/powerpc/kernel/power6-pmu.c
@@ -41,9 +41,9 @@
41#define MMCR1_NESTSEL_SH 45 41#define MMCR1_NESTSEL_SH 45
42#define MMCR1_NESTSEL_MSK 0x7 42#define MMCR1_NESTSEL_MSK 0x7
43#define MMCR1_NESTSEL(m) (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK) 43#define MMCR1_NESTSEL(m) (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK)
44#define MMCR1_PMC1_LLA ((u64)1 << 44) 44#define MMCR1_PMC1_LLA (1ul << 44)
45#define MMCR1_PMC1_LLA_VALUE ((u64)1 << 39) 45#define MMCR1_PMC1_LLA_VALUE (1ul << 39)
46#define MMCR1_PMC1_ADDR_SEL ((u64)1 << 35) 46#define MMCR1_PMC1_ADDR_SEL (1ul << 35)
47#define MMCR1_PMC1SEL_SH 24 47#define MMCR1_PMC1SEL_SH 24
48#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8) 48#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
49#define MMCR1_PMCSEL_MSK 0xff 49#define MMCR1_PMCSEL_MSK 0xff
@@ -173,10 +173,10 @@ static int power6_marked_instr_event(u64 event)
173 * Assign PMC numbers and compute MMCR1 value for a set of events 173 * Assign PMC numbers and compute MMCR1 value for a set of events
174 */ 174 */
175static int p6_compute_mmcr(u64 event[], int n_ev, 175static int p6_compute_mmcr(u64 event[], int n_ev,
176 unsigned int hwc[], u64 mmcr[]) 176 unsigned int hwc[], unsigned long mmcr[])
177{ 177{
178 u64 mmcr1 = 0; 178 unsigned long mmcr1 = 0;
179 u64 mmcra = 0; 179 unsigned long mmcra = 0;
180 int i; 180 int i;
181 unsigned int pmc, ev, b, u, s, psel; 181 unsigned int pmc, ev, b, u, s, psel;
182 unsigned int ttmset = 0; 182 unsigned int ttmset = 0;
@@ -215,7 +215,7 @@ static int p6_compute_mmcr(u64 event[], int n_ev,
215 /* check for conflict on this byte of event bus */ 215 /* check for conflict on this byte of event bus */
216 if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u) 216 if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u)
217 return -1; 217 return -1;
218 mmcr1 |= (u64)u << MMCR1_TTMSEL_SH(b); 218 mmcr1 |= (unsigned long)u << MMCR1_TTMSEL_SH(b);
219 ttmset |= 1 << b; 219 ttmset |= 1 << b;
220 if (u == 5) { 220 if (u == 5) {
221 /* Nest events have a further mux */ 221 /* Nest events have a further mux */
@@ -224,7 +224,7 @@ static int p6_compute_mmcr(u64 event[], int n_ev,
224 MMCR1_NESTSEL(mmcr1) != s) 224 MMCR1_NESTSEL(mmcr1) != s)
225 return -1; 225 return -1;
226 ttmset |= 0x10; 226 ttmset |= 0x10;
227 mmcr1 |= (u64)s << MMCR1_NESTSEL_SH; 227 mmcr1 |= (unsigned long)s << MMCR1_NESTSEL_SH;
228 } 228 }
229 if (0x30 <= psel && psel <= 0x3d) { 229 if (0x30 <= psel && psel <= 0x3d) {
230 /* these need the PMCx_ADDR_SEL bits */ 230 /* these need the PMCx_ADDR_SEL bits */
@@ -243,7 +243,7 @@ static int p6_compute_mmcr(u64 event[], int n_ev,
243 if (power6_marked_instr_event(event[i])) 243 if (power6_marked_instr_event(event[i]))
244 mmcra |= MMCRA_SAMPLE_ENABLE; 244 mmcra |= MMCRA_SAMPLE_ENABLE;
245 if (pmc < 4) 245 if (pmc < 4)
246 mmcr1 |= (u64)psel << MMCR1_PMCSEL_SH(pmc); 246 mmcr1 |= (unsigned long)psel << MMCR1_PMCSEL_SH(pmc);
247 } 247 }
248 mmcr[0] = 0; 248 mmcr[0] = 0;
249 if (pmc_inuse & 1) 249 if (pmc_inuse & 1)
@@ -265,10 +265,11 @@ static int p6_compute_mmcr(u64 event[], int n_ev,
265 * 20-23, 24-27, 28-31 ditto for bytes 1, 2, 3 265 * 20-23, 24-27, 28-31 ditto for bytes 1, 2, 3
266 * 32-34 select field: nest (subunit) event selector 266 * 32-34 select field: nest (subunit) event selector
267 */ 267 */
268static int p6_get_constraint(u64 event, u64 *maskp, u64 *valp) 268static int p6_get_constraint(u64 event, unsigned long *maskp,
269 unsigned long *valp)
269{ 270{
270 int pmc, byte, sh, subunit; 271 int pmc, byte, sh, subunit;
271 u64 mask = 0, value = 0; 272 unsigned long mask = 0, value = 0;
272 273
273 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 274 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
274 if (pmc) { 275 if (pmc) {
@@ -282,11 +283,11 @@ static int p6_get_constraint(u64 event, u64 *maskp, u64 *valp)
282 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; 283 byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
283 sh = byte * 4 + (16 - PM_UNIT_SH); 284 sh = byte * 4 + (16 - PM_UNIT_SH);
284 mask |= PM_UNIT_MSKS << sh; 285 mask |= PM_UNIT_MSKS << sh;
285 value |= (u64)(event & PM_UNIT_MSKS) << sh; 286 value |= (unsigned long)(event & PM_UNIT_MSKS) << sh;
286 if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) { 287 if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) {
287 subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK; 288 subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
288 mask |= (u64)PM_SUBUNIT_MSK << 32; 289 mask |= (unsigned long)PM_SUBUNIT_MSK << 32;
289 value |= (u64)subunit << 32; 290 value |= (unsigned long)subunit << 32;
290 } 291 }
291 } 292 }
292 if (pmc <= 4) { 293 if (pmc <= 4) {
@@ -458,7 +459,7 @@ static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[])
458 return nalt; 459 return nalt;
459} 460}
460 461
461static void p6_disable_pmc(unsigned int pmc, u64 mmcr[]) 462static void p6_disable_pmc(unsigned int pmc, unsigned long mmcr[])
462{ 463{
463 /* Set PMCxSEL to 0 to disable PMCx */ 464 /* Set PMCxSEL to 0 to disable PMCx */
464 if (pmc <= 3) 465 if (pmc <= 3)
@@ -516,17 +517,17 @@ static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
516}; 517};
517 518
518struct power_pmu power6_pmu = { 519struct power_pmu power6_pmu = {
519 .n_counter = 6, 520 .n_counter = 6,
520 .max_alternatives = MAX_ALT, 521 .max_alternatives = MAX_ALT,
521 .add_fields = 0x1555, 522 .add_fields = 0x1555,
522 .test_adder = 0x3000, 523 .test_adder = 0x3000,
523 .compute_mmcr = p6_compute_mmcr, 524 .compute_mmcr = p6_compute_mmcr,
524 .get_constraint = p6_get_constraint, 525 .get_constraint = p6_get_constraint,
525 .get_alternatives = p6_get_alternatives, 526 .get_alternatives = p6_get_alternatives,
526 .disable_pmc = p6_disable_pmc, 527 .disable_pmc = p6_disable_pmc,
527 .limited_pmc_event = p6_limited_pmc_event, 528 .limited_pmc_event = p6_limited_pmc_event,
528 .flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR, 529 .flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR,
529 .n_generic = ARRAY_SIZE(power6_generic_events), 530 .n_generic = ARRAY_SIZE(power6_generic_events),
530 .generic_events = power6_generic_events, 531 .generic_events = power6_generic_events,
531 .cache_events = &power6_cache_events, 532 .cache_events = &power6_cache_events,
532}; 533};
diff --git a/arch/powerpc/kernel/power7-pmu.c b/arch/powerpc/kernel/power7-pmu.c
index b72e7a19d054..658d1ae436a0 100644
--- a/arch/powerpc/kernel/power7-pmu.c
+++ b/arch/powerpc/kernel/power7-pmu.c
@@ -71,10 +71,11 @@
71 * 0-9: Count of events needing PMC1..PMC5 71 * 0-9: Count of events needing PMC1..PMC5
72 */ 72 */
73 73
74static int power7_get_constraint(u64 event, u64 *maskp, u64 *valp) 74static int power7_get_constraint(u64 event, unsigned long *maskp,
75 unsigned long *valp)
75{ 76{
76 int pmc, sh; 77 int pmc, sh;
77 u64 mask = 0, value = 0; 78 unsigned long mask = 0, value = 0;
78 79
79 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 80 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
80 if (pmc) { 81 if (pmc) {
@@ -224,10 +225,10 @@ static int power7_marked_instr_event(u64 event)
224} 225}
225 226
226static int power7_compute_mmcr(u64 event[], int n_ev, 227static int power7_compute_mmcr(u64 event[], int n_ev,
227 unsigned int hwc[], u64 mmcr[]) 228 unsigned int hwc[], unsigned long mmcr[])
228{ 229{
229 u64 mmcr1 = 0; 230 unsigned long mmcr1 = 0;
230 u64 mmcra = 0; 231 unsigned long mmcra = 0;
231 unsigned int pmc, unit, combine, l2sel, psel; 232 unsigned int pmc, unit, combine, l2sel, psel;
232 unsigned int pmc_inuse = 0; 233 unsigned int pmc_inuse = 0;
233 int i; 234 int i;
@@ -265,11 +266,14 @@ static int power7_compute_mmcr(u64 event[], int n_ev,
265 --pmc; 266 --pmc;
266 } 267 }
267 if (pmc <= 3) { 268 if (pmc <= 3) {
268 mmcr1 |= (u64) unit << (MMCR1_TTM0SEL_SH - 4 * pmc); 269 mmcr1 |= (unsigned long) unit
269 mmcr1 |= (u64) combine << (MMCR1_PMC1_COMBINE_SH - pmc); 270 << (MMCR1_TTM0SEL_SH - 4 * pmc);
271 mmcr1 |= (unsigned long) combine
272 << (MMCR1_PMC1_COMBINE_SH - pmc);
270 mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc); 273 mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
271 if (unit == 6) /* L2 events */ 274 if (unit == 6) /* L2 events */
272 mmcr1 |= (u64) l2sel << MMCR1_L2SEL_SH; 275 mmcr1 |= (unsigned long) l2sel
276 << MMCR1_L2SEL_SH;
273 } 277 }
274 if (power7_marked_instr_event(event[i])) 278 if (power7_marked_instr_event(event[i]))
275 mmcra |= MMCRA_SAMPLE_ENABLE; 279 mmcra |= MMCRA_SAMPLE_ENABLE;
@@ -287,10 +291,10 @@ static int power7_compute_mmcr(u64 event[], int n_ev,
287 return 0; 291 return 0;
288} 292}
289 293
290static void power7_disable_pmc(unsigned int pmc, u64 mmcr[]) 294static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
291{ 295{
292 if (pmc <= 3) 296 if (pmc <= 3)
293 mmcr[1] &= ~(0xffULL << MMCR1_PMCSEL_SH(pmc)); 297 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
294} 298}
295 299
296static int power7_generic_events[] = { 300static int power7_generic_events[] = {
@@ -343,15 +347,15 @@ static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
343}; 347};
344 348
345struct power_pmu power7_pmu = { 349struct power_pmu power7_pmu = {
346 .n_counter = 6, 350 .n_counter = 6,
347 .max_alternatives = MAX_ALT + 1, 351 .max_alternatives = MAX_ALT + 1,
348 .add_fields = 0x1555ull, 352 .add_fields = 0x1555ul,
349 .test_adder = 0x3000ull, 353 .test_adder = 0x3000ul,
350 .compute_mmcr = power7_compute_mmcr, 354 .compute_mmcr = power7_compute_mmcr,
351 .get_constraint = power7_get_constraint, 355 .get_constraint = power7_get_constraint,
352 .get_alternatives = power7_get_alternatives, 356 .get_alternatives = power7_get_alternatives,
353 .disable_pmc = power7_disable_pmc, 357 .disable_pmc = power7_disable_pmc,
354 .n_generic = ARRAY_SIZE(power7_generic_events), 358 .n_generic = ARRAY_SIZE(power7_generic_events),
355 .generic_events = power7_generic_events, 359 .generic_events = power7_generic_events,
356 .cache_events = &power7_cache_events, 360 .cache_events = &power7_cache_events,
357}; 361};
diff --git a/arch/powerpc/kernel/ppc970-pmu.c b/arch/powerpc/kernel/ppc970-pmu.c
index ba0a357a89f4..3ed88333412f 100644
--- a/arch/powerpc/kernel/ppc970-pmu.c
+++ b/arch/powerpc/kernel/ppc970-pmu.c
@@ -183,7 +183,7 @@ static int p970_marked_instr_event(u64 event)
183} 183}
184 184
185/* Masks and values for using events from the various units */ 185/* Masks and values for using events from the various units */
186static u64 unit_cons[PM_LASTUNIT+1][2] = { 186static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
187 [PM_FPU] = { 0xc80000000000ull, 0x040000000000ull }, 187 [PM_FPU] = { 0xc80000000000ull, 0x040000000000ull },
188 [PM_VPU] = { 0xc80000000000ull, 0xc40000000000ull }, 188 [PM_VPU] = { 0xc80000000000ull, 0xc40000000000ull },
189 [PM_ISU] = { 0x080000000000ull, 0x020000000000ull }, 189 [PM_ISU] = { 0x080000000000ull, 0x020000000000ull },
@@ -192,10 +192,11 @@ static u64 unit_cons[PM_LASTUNIT+1][2] = {
192 [PM_STS] = { 0x380000000000ull, 0x310000000000ull }, 192 [PM_STS] = { 0x380000000000ull, 0x310000000000ull },
193}; 193};
194 194
195static int p970_get_constraint(u64 event, u64 *maskp, u64 *valp) 195static int p970_get_constraint(u64 event, unsigned long *maskp,
196 unsigned long *valp)
196{ 197{
197 int pmc, byte, unit, sh, spcsel; 198 int pmc, byte, unit, sh, spcsel;
198 u64 mask = 0, value = 0; 199 unsigned long mask = 0, value = 0;
199 int grp = -1; 200 int grp = -1;
200 201
201 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 202 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
@@ -222,7 +223,7 @@ static int p970_get_constraint(u64 event, u64 *maskp, u64 *valp)
222 grp = byte & 1; 223 grp = byte & 1;
223 /* Set byte lane select field */ 224 /* Set byte lane select field */
224 mask |= 0xfULL << (28 - 4 * byte); 225 mask |= 0xfULL << (28 - 4 * byte);
225 value |= (u64)unit << (28 - 4 * byte); 226 value |= (unsigned long)unit << (28 - 4 * byte);
226 } 227 }
227 if (grp == 0) { 228 if (grp == 0) {
228 /* increment PMC1/2/5/6 field */ 229 /* increment PMC1/2/5/6 field */
@@ -236,7 +237,7 @@ static int p970_get_constraint(u64 event, u64 *maskp, u64 *valp)
236 spcsel = (event >> PM_SPCSEL_SH) & PM_SPCSEL_MSK; 237 spcsel = (event >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
237 if (spcsel) { 238 if (spcsel) {
238 mask |= 3ull << 48; 239 mask |= 3ull << 48;
239 value |= (u64)spcsel << 48; 240 value |= (unsigned long)spcsel << 48;
240 } 241 }
241 *maskp = mask; 242 *maskp = mask;
242 *valp = value; 243 *valp = value;
@@ -257,9 +258,9 @@ static int p970_get_alternatives(u64 event, unsigned int flags, u64 alt[])
257} 258}
258 259
259static int p970_compute_mmcr(u64 event[], int n_ev, 260static int p970_compute_mmcr(u64 event[], int n_ev,
260 unsigned int hwc[], u64 mmcr[]) 261 unsigned int hwc[], unsigned long mmcr[])
261{ 262{
262 u64 mmcr0 = 0, mmcr1 = 0, mmcra = 0; 263 unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0;
263 unsigned int pmc, unit, byte, psel; 264 unsigned int pmc, unit, byte, psel;
264 unsigned int ttm, grp; 265 unsigned int ttm, grp;
265 unsigned int pmc_inuse = 0; 266 unsigned int pmc_inuse = 0;
@@ -320,7 +321,7 @@ static int p970_compute_mmcr(u64 event[], int n_ev,
320 continue; 321 continue;
321 ttm = unitmap[i]; 322 ttm = unitmap[i];
322 ++ttmuse[(ttm >> 2) & 1]; 323 ++ttmuse[(ttm >> 2) & 1];
323 mmcr1 |= (u64)(ttm & ~4) << MMCR1_TTM1SEL_SH; 324 mmcr1 |= (unsigned long)(ttm & ~4) << MMCR1_TTM1SEL_SH;
324 } 325 }
325 /* Check only one unit per TTMx */ 326 /* Check only one unit per TTMx */
326 if (ttmuse[0] > 1 || ttmuse[1] > 1) 327 if (ttmuse[0] > 1 || ttmuse[1] > 1)
@@ -340,7 +341,8 @@ static int p970_compute_mmcr(u64 event[], int n_ev,
340 if (unit == PM_LSU1L && byte >= 2) 341 if (unit == PM_LSU1L && byte >= 2)
341 mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte); 342 mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
342 } 343 }
343 mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); 344 mmcr1 |= (unsigned long)ttm
345 << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
344 } 346 }
345 347
346 /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */ 348 /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
@@ -386,7 +388,8 @@ static int p970_compute_mmcr(u64 event[], int n_ev,
386 for (pmc = 0; pmc < 2; ++pmc) 388 for (pmc = 0; pmc < 2; ++pmc)
387 mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc); 389 mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc);
388 for (; pmc < 8; ++pmc) 390 for (; pmc < 8; ++pmc)
389 mmcr1 |= (u64)pmcsel[pmc] << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2)); 391 mmcr1 |= (unsigned long)pmcsel[pmc]
392 << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2));
390 if (pmc_inuse & 1) 393 if (pmc_inuse & 1)
391 mmcr0 |= MMCR0_PMC1CE; 394 mmcr0 |= MMCR0_PMC1CE;
392 if (pmc_inuse & 0xfe) 395 if (pmc_inuse & 0xfe)
@@ -401,7 +404,7 @@ static int p970_compute_mmcr(u64 event[], int n_ev,
401 return 0; 404 return 0;
402} 405}
403 406
404static void p970_disable_pmc(unsigned int pmc, u64 mmcr[]) 407static void p970_disable_pmc(unsigned int pmc, unsigned long mmcr[])
405{ 408{
406 int shift, i; 409 int shift, i;
407 410
@@ -468,15 +471,15 @@ static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
468}; 471};
469 472
470struct power_pmu ppc970_pmu = { 473struct power_pmu ppc970_pmu = {
471 .n_counter = 8, 474 .n_counter = 8,
472 .max_alternatives = 2, 475 .max_alternatives = 2,
473 .add_fields = 0x001100005555ull, 476 .add_fields = 0x001100005555ull,
474 .test_adder = 0x013300000000ull, 477 .test_adder = 0x013300000000ull,
475 .compute_mmcr = p970_compute_mmcr, 478 .compute_mmcr = p970_compute_mmcr,
476 .get_constraint = p970_get_constraint, 479 .get_constraint = p970_get_constraint,
477 .get_alternatives = p970_get_alternatives, 480 .get_alternatives = p970_get_alternatives,
478 .disable_pmc = p970_disable_pmc, 481 .disable_pmc = p970_disable_pmc,
479 .n_generic = ARRAY_SIZE(ppc970_generic_events), 482 .n_generic = ARRAY_SIZE(ppc970_generic_events),
480 .generic_events = ppc970_generic_events, 483 .generic_events = ppc970_generic_events,
481 .cache_events = &ppc970_cache_events, 484 .cache_events = &ppc970_cache_events,
482}; 485};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 18:49:58 -0500