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authorOlof Johansson <olof@lixom.net>2007-11-19 20:24:45 -0500
committerPaul Mackerras <paulus@samba.org>2007-11-19 21:56:31 -0500
commitfbe481756df57673b6acbcd2e139d0d2658f2188 (patch)
treef1981a79330e1eeaa2294516587bf338f4a6476e /arch/powerpc/kernel/vdso64
parent92e21e79a85924ddda00f4678d60bbd8f891a553 (diff)
[POWERPC] vdso: Fixes for cache block sizes
The current VDSO implementation is hardcoded to 128 byte cache blocks, which are only used on IBM's 64-bit processors. Convert it to get the cache block sizes out of vdso_data instead, similar to how the ppc64 in-kernel cache flush does it. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/kernel/vdso64')
-rw-r--r--arch/powerpc/kernel/vdso64/cacheflush.S41
1 files changed, 29 insertions, 12 deletions
diff --git a/arch/powerpc/kernel/vdso64/cacheflush.S b/arch/powerpc/kernel/vdso64/cacheflush.S
index 66a36d3cc6ad..69c5af2b3c96 100644
--- a/arch/powerpc/kernel/vdso64/cacheflush.S
+++ b/arch/powerpc/kernel/vdso64/cacheflush.S
@@ -23,29 +23,46 @@
23 * 23 *
24 * Flushes the data cache & invalidate the instruction cache for the 24 * Flushes the data cache & invalidate the instruction cache for the
25 * provided range [start, end[ 25 * provided range [start, end[
26 *
27 * Note: all CPUs supported by this kernel have a 128 bytes cache
28 * line size so we don't have to peek that info from the datapage
29 */ 26 */
30V_FUNCTION_BEGIN(__kernel_sync_dicache) 27V_FUNCTION_BEGIN(__kernel_sync_dicache)
31 .cfi_startproc 28 .cfi_startproc
32 li r5,127 29 mflr r12
33 andc r6,r3,r5 /* round low to line bdy */ 30 .cfi_register lr,r12
31 mr r11,r3
32 bl V_LOCAL_FUNC(__get_datapage)
33 mtlr r12
34 mr r10,r3
35
36 lwz r7,CFG_DCACHE_BLOCKSZ(r10)
37 addi r5,r7,-1
38 andc r6,r11,r5 /* round low to line bdy */
34 subf r8,r6,r4 /* compute length */ 39 subf r8,r6,r4 /* compute length */
35 add r8,r8,r5 /* ensure we get enough */ 40 add r8,r8,r5 /* ensure we get enough */
36 srwi. r8,r8,7 /* compute line count */ 41 lwz r9,CFG_DCACHE_LOGBLOCKSZ(r10)
42 srw. r8,r8,r9 /* compute line count */
37 crclr cr0*4+so 43 crclr cr0*4+so
38 beqlr /* nothing to do? */ 44 beqlr /* nothing to do? */
39 mtctr r8 45 mtctr r8
40 mr r3,r6 461: dcbst 0,r6
411: dcbst 0,r3 47 add r6,r6,r7
42 addi r3,r3,128
43 bdnz 1b 48 bdnz 1b
44 sync 49 sync
50
51/* Now invalidate the instruction cache */
52
53 lwz r7,CFG_ICACHE_BLOCKSZ(r10)
54 addi r5,r7,-1
55 andc r6,r11,r5 /* round low to line bdy */
56 subf r8,r6,r4 /* compute length */
57 add r8,r8,r5
58 lwz r9,CFG_ICACHE_LOGBLOCKSZ(r10)
59 srw. r8,r8,r9 /* compute line count */
60 crclr cr0*4+so
61 beqlr /* nothing to do? */
45 mtctr r8 62 mtctr r8
461: icbi 0,r6 632: icbi 0,r6
47 addi r6,r6,128 64 add r6,r6,r7
48 bdnz 1b 65 bdnz 2b
49 isync 66 isync
50 li r3,0 67 li r3,0
51 blr 68 blr