powerpc/fsl-booke: Handle L1 D-cache parity error correctly on e500mc

If the L1 D-Cache is in write shadow mode the HW will auto-recover the
error.  However we might still log the error and cause a machine check
(if L1CSR0[CPE] - Cache error checking enable).  We should only treat
the non-write shadow case as non-recoverable.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 8 insertions, 1 deletions

diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index f19d9777d3c1..4e5908264d1a 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -457,7 +457,14 @@ int machine_check_e500mc(struct pt_regs *regs)
 
         if (reason & MCSR_DCPERR_MC) {
                 printk("Data Cache Parity Error\n");
-                recoverable = 0;
+
+                /*
+                 * In write shadow mode we auto-recover from the error, but it
+                 * may still get logged and cause a machine check.  We should
+                 * only treat the non-write shadow case as non-recoverable.
+                 */
+                if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
+                        recoverable = 0;
         }
 
         if (reason & MCSR_L2MMU_MHIT) {