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authorDave Kleikamp <shaggy@linux.vnet.ibm.com>2010-02-08 06:50:57 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2010-02-16 22:03:16 -0500
commit172ae2e7f8ff9053905a36672453a6d2ff95b182 (patch)
tree2469b6923a4d7756930ac9c83e8b8fc9bfcdcbe0 /arch/powerpc/kernel/ptrace.c
parent789c299ca280f96368c0296b739e89c0bb232f8a (diff)
powerpc/booke: Introduce new CONFIG options for advanced debug registers
powerpc/booke: Introduce new CONFIG options for advanced debug registers From: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Introduce new config options to simplify the ifdefs pertaining to the advanced debug registers for booke and 40x processors: CONFIG_PPC_ADV_DEBUG_REGS - boolean: true for dac-based processors CONFIG_PPC_ADV_DEBUG_IACS - number of IAC registers CONFIG_PPC_ADV_DEBUG_DACS - number of DAC registers CONFIG_PPC_ADV_DEBUG_DVCS - number of DVC registers CONFIG_PPC_ADV_DEBUG_DAC_RANGE - DAC ranges supported Beginning conservatively, since I only have the facilities to test 440 hardware. I believe all 40x and booke platforms support at least 2 IAC and 2 DAC registers. For 440, 4 IAC and 2 DVC registers are enabled, as well as the DAC ranges. Signed-off-by: Dave Kleikamp <shaggy@linux.vnet.ibm.com> Acked-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel/ptrace.c')
-rw-r--r--arch/powerpc/kernel/ptrace.c18
1 files changed, 7 insertions, 11 deletions
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index ef149880c145..292c81432014 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -46,7 +46,7 @@
46/* 46/*
47 * Set of msr bits that gdb can change on behalf of a process. 47 * Set of msr bits that gdb can change on behalf of a process.
48 */ 48 */
49#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) 49#ifdef CONFIG_PPC_ADV_DEBUG_REGS
50#define MSR_DEBUGCHANGE 0 50#define MSR_DEBUGCHANGE 0
51#else 51#else
52#define MSR_DEBUGCHANGE (MSR_SE | MSR_BE) 52#define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
@@ -703,7 +703,7 @@ void user_enable_single_step(struct task_struct *task)
703 struct pt_regs *regs = task->thread.regs; 703 struct pt_regs *regs = task->thread.regs;
704 704
705 if (regs != NULL) { 705 if (regs != NULL) {
706#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) 706#ifdef CONFIG_PPC_ADV_DEBUG_REGS
707 task->thread.dbcr0 &= ~DBCR0_BT; 707 task->thread.dbcr0 &= ~DBCR0_BT;
708 task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; 708 task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
709 regs->msr |= MSR_DE; 709 regs->msr |= MSR_DE;
@@ -720,7 +720,7 @@ void user_enable_block_step(struct task_struct *task)
720 struct pt_regs *regs = task->thread.regs; 720 struct pt_regs *regs = task->thread.regs;
721 721
722 if (regs != NULL) { 722 if (regs != NULL) {
723#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) 723#ifdef CONFIG_PPC_ADV_DEBUG_REGS
724 task->thread.dbcr0 &= ~DBCR0_IC; 724 task->thread.dbcr0 &= ~DBCR0_IC;
725 task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT; 725 task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT;
726 regs->msr |= MSR_DE; 726 regs->msr |= MSR_DE;
@@ -737,7 +737,7 @@ void user_disable_single_step(struct task_struct *task)
737 struct pt_regs *regs = task->thread.regs; 737 struct pt_regs *regs = task->thread.regs;
738 738
739 if (regs != NULL) { 739 if (regs != NULL) {
740#if defined(CONFIG_BOOKE) 740#ifdef CONFIG_PPC_ADV_DEBUG_REGS
741 /* If DAC don't clear DBCRO_IDM or MSR_DE */ 741 /* If DAC don't clear DBCRO_IDM or MSR_DE */
742 if (task->thread.dabr) 742 if (task->thread.dabr)
743 task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_BT); 743 task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_BT);
@@ -745,9 +745,6 @@ void user_disable_single_step(struct task_struct *task)
745 task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_BT | DBCR0_IDM); 745 task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_BT | DBCR0_IDM);
746 regs->msr &= ~MSR_DE; 746 regs->msr &= ~MSR_DE;
747 } 747 }
748#elif defined(CONFIG_40x)
749 task->thread.dbcr0 &= ~(DBCR0_IC | DBCR0_BT | DBCR0_IDM);
750 regs->msr &= ~MSR_DE;
751#else 748#else
752 regs->msr &= ~(MSR_SE | MSR_BE); 749 regs->msr &= ~(MSR_SE | MSR_BE);
753#endif 750#endif
@@ -769,7 +766,7 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
769 if ((data & ~0x7UL) >= TASK_SIZE) 766 if ((data & ~0x7UL) >= TASK_SIZE)
770 return -EIO; 767 return -EIO;
771 768
772#ifndef CONFIG_BOOKE 769#ifndef CONFIG_PPC_ADV_DEBUG_REGS
773 770
774 /* For processors using DABR (i.e. 970), the bottom 3 bits are flags. 771 /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
775 * It was assumed, on previous implementations, that 3 bits were 772 * It was assumed, on previous implementations, that 3 bits were
@@ -790,8 +787,7 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
790 /* Move contents to the DABR register */ 787 /* Move contents to the DABR register */
791 task->thread.dabr = data; 788 task->thread.dabr = data;
792 789
793#endif 790#else /* CONFIG_PPC_ADV_DEBUG_REGS */
794#if defined(CONFIG_BOOKE)
795 791
796 /* As described above, it was assumed 3 bits were passed with the data 792 /* As described above, it was assumed 3 bits were passed with the data
797 * address, but we will assume only the mode bits will be passed 793 * address, but we will assume only the mode bits will be passed
@@ -824,7 +820,7 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
824 task->thread.dbcr0 |= DBSR_DAC1W; 820 task->thread.dbcr0 |= DBSR_DAC1W;
825 821
826 task->thread.regs->msr |= MSR_DE; 822 task->thread.regs->msr |= MSR_DE;
827#endif 823#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
828 return 0; 824 return 0;
829} 825}
830 826