Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc

Pull powerpc updates from Benjamin Herrenschmidt:
 "The bulk of this is LE updates.  One should now be able to build an LE
  kernel and even run some things in it.

  I'm still sitting on a handful of patches to enable the new ABI that I
  *might* still send this merge window around, but due to the
  incertainty (they are pretty fresh) I want to keep them separate.

  Other notable changes are some infrastructure bits to better handle
  PCI pass-through under KVM, some bits and pieces added to the new
  PowerNV platform support such as access to the CPU SCOM bus via sysfs,
  and support for EEH error handling on PHB3 (Power8 PCIe).

  We also grew arch_get_random_long() for both pseries and powernv when
  running on P7+ and P8, exploiting the HW rng.

  And finally various embedded updates from freescale"

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (154 commits)
  powerpc: Fix fatal SLB miss when restoring PPR
  powerpc/powernv: Reserve the correct PE number
  powerpc/powernv: Add PE to its own PELTV
  powerpc/powernv: Add support for indirect XSCOM via debugfs
  powerpc/scom: Improve debugfs interface
  powerpc/scom: Enable 64-bit addresses
  powerpc/boot: Properly handle the base "of" boot wrapper
  powerpc/bpf: Support MOD operation
  powerpc/bpf: Fix DIVWU instruction opcode
  of: Move definition of of_find_next_cache_node into common code.
  powerpc: Remove big endianness assumption in of_find_next_cache_node
  powerpc/tm: Remove interrupt disable in __switch_to()
  powerpc: word-at-a-time optimization for 64-bit Little Endian
  powerpc/bpf: BPF JIT compiler for 64-bit Little Endian
  powerpc: Only save/restore SDR1 if in hypervisor mode
  powerpc/pmu: Fix ADB_PMU_LED_IDE dependencies
  powerpc/nvram: Fix endian issue when using the partition length
  powerpc/nvram: Fix endian issue when reading the NVRAM size
  powerpc/nvram: Scan partitions only once
  powerpc/mpc512x: remove unnecessary #if
  ...

1 files changed, 35 insertions, 32 deletions

diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 96d2fdf3aa9e..75c2d1009985 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -314,28 +314,28 @@ static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
  */
 static void set_debug_reg_defaults(struct thread_struct *thread)
 {
-        thread->iac1 = thread->iac2 = 0;
+        thread->debug.iac1 = thread->debug.iac2 = 0;
 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
-        thread->iac3 = thread->iac4 = 0;
+        thread->debug.iac3 = thread->debug.iac4 = 0;
 #endif
-        thread->dac1 = thread->dac2 = 0;
+        thread->debug.dac1 = thread->debug.dac2 = 0;
 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
-        thread->dvc1 = thread->dvc2 = 0;
+        thread->debug.dvc1 = thread->debug.dvc2 = 0;
 #endif
-        thread->dbcr0 = 0;
+        thread->debug.dbcr0 = 0;
 #ifdef CONFIG_BOOKE
         /*
          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
          */
-        thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |   \
+        thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
                         DBCR1_IAC3US | DBCR1_IAC4US;
         /*
          * Force Data Address Compare User/Supervisor bits to be User-only
          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
          */
-        thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
+        thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 #else
-        thread->dbcr1 = 0;
+        thread->debug.dbcr1 = 0;
 #endif
 }
 
@@ -348,22 +348,22 @@ static void prime_debug_regs(struct thread_struct *thread)
          */
         mtmsr(mfmsr() & ~MSR_DE);
 
-        mtspr(SPRN_IAC1, thread->iac1);
-        mtspr(SPRN_IAC2, thread->iac2);
+        mtspr(SPRN_IAC1, thread->debug.iac1);
+        mtspr(SPRN_IAC2, thread->debug.iac2);
 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
-        mtspr(SPRN_IAC3, thread->iac3);
-        mtspr(SPRN_IAC4, thread->iac4);
+        mtspr(SPRN_IAC3, thread->debug.iac3);
+        mtspr(SPRN_IAC4, thread->debug.iac4);
 #endif
-        mtspr(SPRN_DAC1, thread->dac1);
-        mtspr(SPRN_DAC2, thread->dac2);
+        mtspr(SPRN_DAC1, thread->debug.dac1);
+        mtspr(SPRN_DAC2, thread->debug.dac2);
 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
-        mtspr(SPRN_DVC1, thread->dvc1);
-        mtspr(SPRN_DVC2, thread->dvc2);
+        mtspr(SPRN_DVC1, thread->debug.dvc1);
+        mtspr(SPRN_DVC2, thread->debug.dvc2);
 #endif
-        mtspr(SPRN_DBCR0, thread->dbcr0);
-        mtspr(SPRN_DBCR1, thread->dbcr1);
+        mtspr(SPRN_DBCR0, thread->debug.dbcr0);
+        mtspr(SPRN_DBCR1, thread->debug.dbcr1);
 #ifdef CONFIG_BOOKE
-        mtspr(SPRN_DBCR2, thread->dbcr2);
+        mtspr(SPRN_DBCR2, thread->debug.dbcr2);
 #endif
 }
 /*
@@ -371,12 +371,13 @@ static void prime_debug_regs(struct thread_struct *thread)
  * debug registers, set the debug registers from the values
  * stored in the new thread.
  */
-static void switch_booke_debug_regs(struct thread_struct *new_thread)
+void switch_booke_debug_regs(struct thread_struct *new_thread)
 {
-        if ((current->thread.dbcr0 & DBCR0_IDM)
-                || (new_thread->dbcr0 & DBCR0_IDM))
+        if ((current->thread.debug.dbcr0 & DBCR0_IDM)
+                || (new_thread->debug.dbcr0 & DBCR0_IDM))
                         prime_debug_regs(new_thread);
 }
+EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 static void set_debug_reg_defaults(struct thread_struct *thread)
@@ -596,12 +597,13 @@ struct task_struct *__switch_to(struct task_struct *prev,
         struct task_struct *new)
 {
         struct thread_struct *new_thread, *old_thread;
-        unsigned long flags;
         struct task_struct *last;
 #ifdef CONFIG_PPC_BOOK3S_64
         struct ppc64_tlb_batch *batch;
 #endif
 
+        WARN_ON(!irqs_disabled());
+
         /* Back up the TAR across context switches.
          * Note that the TAR is not available for use in the kernel.  (To
          * provide this, the TAR should be backed up/restored on exception
@@ -721,8 +723,6 @@ struct task_struct *__switch_to(struct task_struct *prev,
         }
 #endif /* CONFIG_PPC_BOOK3S_64 */
 
-        local_irq_save(flags);
-
         /*
          * We can't take a PMU exception inside _switch() since there is a
          * window where the kernel stack SLB and the kernel stack are out
@@ -742,8 +742,6 @@ struct task_struct *__switch_to(struct task_struct *prev,
         }
 #endif /* CONFIG_PPC_BOOK3S_64 */
 
-        local_irq_restore(flags);
-
         return last;
 }
 
@@ -1008,6 +1006,11 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
         p->thread.ptrace_bps[0] = NULL;
 #endif
 
+        p->thread.fp_save_area = NULL;
+#ifdef CONFIG_ALTIVEC
+        p->thread.vr_save_area = NULL;
+#endif
+
 #ifdef CONFIG_PPC_STD_MMU_64
         if (mmu_has_feature(MMU_FTR_SLB)) {
                 unsigned long sp_vsid;
@@ -1113,12 +1116,12 @@ void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
 #ifdef CONFIG_VSX
         current->thread.used_vsr = 0;
 #endif
-        memset(current->thread.fpr, 0, sizeof(current->thread.fpr));
-        current->thread.fpscr.val = 0;
+        memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
+        current->thread.fp_save_area = NULL;
 #ifdef CONFIG_ALTIVEC
-        memset(current->thread.vr, 0, sizeof(current->thread.vr));
-        memset(&current->thread.vscr, 0, sizeof(current->thread.vscr));
-        current->thread.vscr.u[3] = 0x00010000; /* Java mode disabled */
+        memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
+        current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
+        current->thread.vr_save_area = NULL;
         current->thread.vrsave = 0;
         current->thread.used_vr = 0;
 #endif /* CONFIG_ALTIVEC */