perf_counter: powerpc: Implement generalized cache events for POWER processors

This adds tables of event codes for the generalized cache events for
all the currently supported powerpc processors: POWER{4,5,5+,6,7} and
PPC970*, plus powerpc-specific code to use these tables when a
generalized cache event is requested.

Signed-off-by: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
LKML-Reference: <18992.36430.933526.742969@drongo.ozlabs.ibm.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

1 files changed, 44 insertions, 2 deletions

diff --git a/arch/powerpc/kernel/power6-pmu.c b/arch/powerpc/kernel/power6-pmu.c
index cd4fbe06c35d..4da707866097 100644
--- a/arch/powerpc/kernel/power6-pmu.c
+++ b/arch/powerpc/kernel/power6-pmu.c
@@ -474,6 +474,47 @@ static int power6_generic_events[] = {
         [PERF_COUNT_BRANCH_MISSES] = 0x400052,          /* BR_MPRED */
 };
 
+#define C(x)    PERF_COUNT_HW_CACHE_##x
+
+/*
+ * Table of generalized cache-related events.
+ * 0 means not supported, -1 means nonsensical, other values
+ * are event codes.
+ * The "DTLB" and "ITLB" events relate to the DERAT and IERAT.
+ */
+static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
+        [C(L1D)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x80082,        0x80080         },
+                [C(OP_WRITE)] = {       0x80086,        0x80088         },
+                [C(OP_PREFETCH)] = {    0x810a4,        0               },
+        },
+        [C(L1I)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x100056        },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    0x4008c,        0               },
+        },
+        [C(L2)] = {             /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x150730,       0x250532        },
+                [C(OP_WRITE)] = {       0x250432,       0x150432        },
+                [C(OP_PREFETCH)] = {    0x810a6,        0               },
+        },
+        [C(DTLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x20000e        },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    -1,             -1              },
+        },
+        [C(ITLB)] = {           /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0,              0x420ce         },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    -1,             -1              },
+        },
+        [C(BPU)] = {            /*      RESULT_ACCESS   RESULT_MISS */
+                [C(OP_READ)] = {        0x430e6,        0x400052        },
+                [C(OP_WRITE)] = {       -1,             -1              },
+                [C(OP_PREFETCH)] = {    -1,             -1              },
+        },
+};
+
 struct power_pmu power6_pmu = {
         .n_counter = 6,
         .max_alternatives = MAX_ALT,
@@ -483,8 +524,9 @@ struct power_pmu power6_pmu = {
         .get_constraint = p6_get_constraint,
         .get_alternatives = p6_get_alternatives,
         .disable_pmc = p6_disable_pmc,
+        .limited_pmc_event = p6_limited_pmc_event,
+        .flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR,
         .n_generic = ARRAY_SIZE(power6_generic_events),
         .generic_events = power6_generic_events,
-        .flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR,
-        .limited_pmc_event = p6_limited_pmc_event,
+        .cache_events = &power6_cache_events,
 };