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authorPaul Mackerras <paulus@samba.org>2009-06-17 07:52:09 -0400
committerIngo Molnar <mingo@elte.hu>2009-06-18 05:11:45 -0400
commit079b3c569c87819e7a19d9b9f51d4746fc47bf9a (patch)
tree63dd236c582eebebb0667a3e5235b02b14c850be /arch/powerpc/kernel/power5+-pmu.c
parent448d64f8f4c147db466c549550767cc515a4d34c (diff)
perf_counter: powerpc: Change how processor-specific back-ends get selected
At present, the powerpc generic (processor-independent) perf_counter code has list of processor back-end modules, and at initialization, it looks at the PVR (processor version register) and has a switch statement to select a suitable processor-specific back-end. This is going to become inconvenient as we add more processor-specific back-ends, so this inverts the order: now each back-end checks whether it applies to the current processor, and registers itself if so. Furthermore, instead of looking at the PVR, back-ends now check the cur_cpu_spec->oprofile_cpu_type string and match on that. Lastly, each back-end now specifies a name for itself so the core can print a nice message when a back-end registers itself. This doesn't provide any support for unregistering back-ends, but that wouldn't be hard to do and would allow back-ends to be modules. Signed-off-by: Paul Mackerras <paulus@samba.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: linuxppc-dev@ozlabs.org Cc: benh@kernel.crashing.org LKML-Reference: <19000.55529.762227.518531@cargo.ozlabs.ibm.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/powerpc/kernel/power5+-pmu.c')
-rw-r--r--arch/powerpc/kernel/power5+-pmu.c16
1 files changed, 15 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/power5+-pmu.c b/arch/powerpc/kernel/power5+-pmu.c
index aef144d503b0..f4adca8e98a4 100644
--- a/arch/powerpc/kernel/power5+-pmu.c
+++ b/arch/powerpc/kernel/power5+-pmu.c
@@ -10,7 +10,9 @@
10 */ 10 */
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/perf_counter.h> 12#include <linux/perf_counter.h>
13#include <linux/string.h>
13#include <asm/reg.h> 14#include <asm/reg.h>
15#include <asm/cputable.h>
14 16
15/* 17/*
16 * Bits in event code for POWER5+ (POWER5 GS) and POWER5++ (POWER5 GS DD3) 18 * Bits in event code for POWER5+ (POWER5 GS) and POWER5++ (POWER5 GS DD3)
@@ -657,7 +659,8 @@ static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
657 }, 659 },
658}; 660};
659 661
660struct power_pmu power5p_pmu = { 662static struct power_pmu power5p_pmu = {
663 .name = "POWER5+/++",
661 .n_counter = 6, 664 .n_counter = 6,
662 .max_alternatives = MAX_ALT, 665 .max_alternatives = MAX_ALT,
663 .add_fields = 0x7000000000055ul, 666 .add_fields = 0x7000000000055ul,
@@ -672,3 +675,14 @@ struct power_pmu power5p_pmu = {
672 .generic_events = power5p_generic_events, 675 .generic_events = power5p_generic_events,
673 .cache_events = &power5p_cache_events, 676 .cache_events = &power5p_cache_events,
674}; 677};
678
679static int init_power5p_pmu(void)
680{
681 if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5+")
682 && strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5++"))
683 return -ENODEV;
684
685 return register_power_pmu(&power5p_pmu);
686}
687
688arch_initcall(init_power5p_pmu);