diff options
author | David Gibson <david@gibson.dropbear.id.au> | 2006-01-12 22:56:25 -0500 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2006-01-13 05:16:23 -0500 |
commit | e58c3495e6007af59382540bb21ee941e470d88d (patch) | |
tree | 24b559cb768bfa5cf4bdef69f2943b081a1f5afa /arch/powerpc/kernel/misc_64.S | |
parent | 7e78e5e502d4f220d24c6f738f2fdb078ad33607 (diff) |
[PATCH] powerpc: Cleanup LOADADDR etc. asm macros
This patch consolidates the variety of macros used for loading 32 or
64-bit constants in assembler (LOADADDR, LOADBASE, SET_REG_TO_*). The
idea is to make the set of macros consistent across 32 and 64 bit and
to make it more obvious which is the appropriate one to use in a given
situation. The new macros and their semantics are described in the
comments in ppc_asm.h.
In the process, we change several places that were unnecessarily using
immediate loads on ppc64 to use the GOT/TOC. Likewise we cleanup a
couple of places where we were clumsily subtracting PAGE_OFFSET with
asm instructions to use assemble-time arithmetic or the toreal() macro
instead.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/kernel/misc_64.S')
-rw-r--r-- | arch/powerpc/kernel/misc_64.S | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S index ae48a002f81a..2778cce058e2 100644 --- a/arch/powerpc/kernel/misc_64.S +++ b/arch/powerpc/kernel/misc_64.S | |||
@@ -39,7 +39,7 @@ _GLOBAL(reloc_offset) | |||
39 | mflr r0 | 39 | mflr r0 |
40 | bl 1f | 40 | bl 1f |
41 | 1: mflr r3 | 41 | 1: mflr r3 |
42 | LOADADDR(r4,1b) | 42 | LOAD_REG_IMMEDIATE(r4,1b) |
43 | subf r3,r4,r3 | 43 | subf r3,r4,r3 |
44 | mtlr r0 | 44 | mtlr r0 |
45 | blr | 45 | blr |
@@ -51,7 +51,7 @@ _GLOBAL(add_reloc_offset) | |||
51 | mflr r0 | 51 | mflr r0 |
52 | bl 1f | 52 | bl 1f |
53 | 1: mflr r5 | 53 | 1: mflr r5 |
54 | LOADADDR(r4,1b) | 54 | LOAD_REG_IMMEDIATE(r4,1b) |
55 | subf r5,r4,r5 | 55 | subf r5,r4,r5 |
56 | add r3,r3,r5 | 56 | add r3,r3,r5 |
57 | mtlr r0 | 57 | mtlr r0 |
@@ -498,15 +498,15 @@ _GLOBAL(identify_cpu) | |||
498 | */ | 498 | */ |
499 | _GLOBAL(do_cpu_ftr_fixups) | 499 | _GLOBAL(do_cpu_ftr_fixups) |
500 | /* Get CPU 0 features */ | 500 | /* Get CPU 0 features */ |
501 | LOADADDR(r6,cur_cpu_spec) | 501 | LOAD_REG_IMMEDIATE(r6,cur_cpu_spec) |
502 | sub r6,r6,r3 | 502 | sub r6,r6,r3 |
503 | ld r4,0(r6) | 503 | ld r4,0(r6) |
504 | sub r4,r4,r3 | 504 | sub r4,r4,r3 |
505 | ld r4,CPU_SPEC_FEATURES(r4) | 505 | ld r4,CPU_SPEC_FEATURES(r4) |
506 | /* Get the fixup table */ | 506 | /* Get the fixup table */ |
507 | LOADADDR(r6,__start___ftr_fixup) | 507 | LOAD_REG_IMMEDIATE(r6,__start___ftr_fixup) |
508 | sub r6,r6,r3 | 508 | sub r6,r6,r3 |
509 | LOADADDR(r7,__stop___ftr_fixup) | 509 | LOAD_REG_IMMEDIATE(r7,__stop___ftr_fixup) |
510 | sub r7,r7,r3 | 510 | sub r7,r7,r3 |
511 | /* Do the fixup */ | 511 | /* Do the fixup */ |
512 | 1: cmpld r6,r7 | 512 | 1: cmpld r6,r7 |