[POWERPC] Consolidate feature fixup code

There are currently two versions of the functions for applying the
feature fixups, one for CPU features and one for firmware features. In
addition, they are both in assembly and with separate implementations
for 32 and 64 bits. identify_cpu() is also implemented in assembly and
separately for 32 and 64 bits.

This patch replaces them with a pair of C functions. The call sites are
slightly moved on ppc64 as well to be called from C instead of from
assembly, though it's a very small change, and thus shouldn't cause any
problem.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 0 insertions, 124 deletions

diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index c70e20708a1f..21fd2c662a99 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -246,130 +246,6 @@ _GLOBAL(__flush_dcache_icache)
         isync
         blr
 
-/*
- * identify_cpu and calls setup_cpu
- * In:  r3 = base of the cpu_specs array
- *      r4 = address of cur_cpu_spec
- *      r5 = relocation offset
- */
-_GLOBAL(identify_cpu)
-        mfpvr   r7
-1:
-        lwz     r8,CPU_SPEC_PVR_MASK(r3)
-        and     r8,r8,r7
-        lwz     r9,CPU_SPEC_PVR_VALUE(r3)
-        cmplw   0,r9,r8
-        beq     1f
-        addi    r3,r3,CPU_SPEC_ENTRY_SIZE
-        b       1b
-1:
-        sub     r0,r3,r5
-        std     r0,0(r4)
-        ld      r4,CPU_SPEC_SETUP(r3)
-        cmpdi   0,r4,0
-        add     r4,r4,r5
-        beqlr
-        ld      r4,0(r4)
-        add     r4,r4,r5
-        mtctr   r4
-        /* Calling convention for cpu setup is r3=offset, r4=cur_cpu_spec */
-        mr      r4,r3
-        mr      r3,r5
-        bctr
-
-/*
- * do_cpu_ftr_fixups - goes through the list of CPU feature fixups
- * and writes nop's over sections of code that don't apply for this cpu.
- * r3 = data offset (not changed)
- */
-_GLOBAL(do_cpu_ftr_fixups)
-        /* Get CPU 0 features */
-        LOAD_REG_IMMEDIATE(r6,cur_cpu_spec)
-        sub     r6,r6,r3
-        ld      r4,0(r6)
-        sub     r4,r4,r3
-        ld      r4,CPU_SPEC_FEATURES(r4)
-        /* Get the fixup table */
-        LOAD_REG_IMMEDIATE(r6,__start___ftr_fixup)
-        sub     r6,r6,r3
-        LOAD_REG_IMMEDIATE(r7,__stop___ftr_fixup)
-        sub     r7,r7,r3
-        /* Do the fixup */
-1:      cmpld   r6,r7
-        bgelr
-        addi    r6,r6,32
-        ld      r8,-32(r6)      /* mask */
-        and     r8,r8,r4
-        ld      r9,-24(r6)      /* value */
-        cmpld   r8,r9
-        beq     1b
-        ld      r8,-16(r6)      /* section begin */
-        ld      r9,-8(r6)       /* section end */
-        subf.   r9,r8,r9
-        beq     1b
-        /* write nops over the section of code */
-        /* todo: if large section, add a branch at the start of it */
-        srwi    r9,r9,2
-        mtctr   r9
-        sub     r8,r8,r3
-        lis     r0,0x60000000@h /* nop */
-3:      stw     r0,0(r8)
-        andi.   r10,r4,CPU_FTR_SPLIT_ID_CACHE@l
-        beq     2f
-        dcbst   0,r8            /* suboptimal, but simpler */
-        sync
-        icbi    0,r8
-2:      addi    r8,r8,4
-        bdnz    3b
-        sync                    /* additional sync needed on g4 */
-        isync
-        b       1b
-
-/*
- * do_fw_ftr_fixups - goes through the list of firmware feature fixups
- * and writes nop's over sections of code that don't apply for this firmware.
- * r3 = data offset (not changed)
- */
-_GLOBAL(do_fw_ftr_fixups)
-        /* Get firmware features */
-        LOAD_REG_IMMEDIATE(r6,powerpc_firmware_features)
-        sub     r6,r6,r3
-        ld      r4,0(r6)
-        /* Get the fixup table */
-        LOAD_REG_IMMEDIATE(r6,__start___fw_ftr_fixup)
-        sub     r6,r6,r3
-        LOAD_REG_IMMEDIATE(r7,__stop___fw_ftr_fixup)
-        sub     r7,r7,r3
-        /* Do the fixup */
-1:      cmpld   r6,r7
-        bgelr
-        addi    r6,r6,32
-        ld      r8,-32(r6)      /* mask */
-        and     r8,r8,r4
-        ld      r9,-24(r6)      /* value */
-        cmpld   r8,r9
-        beq     1b
-        ld      r8,-16(r6)      /* section begin */
-        ld      r9,-8(r6)       /* section end */
-        subf.   r9,r8,r9
-        beq     1b
-        /* write nops over the section of code */
-        /* todo: if large section, add a branch at the start of it */
-        srwi    r9,r9,2
-        mtctr   r9
-        sub     r8,r8,r3
-        lis     r0,0x60000000@h /* nop */
-3:      stw     r0,0(r8)
-BEGIN_FTR_SECTION
-        dcbst   0,r8            /* suboptimal, but simpler */
-        sync
-        icbi    0,r8
-END_FTR_SECTION_IFSET(CPU_FTR_SPLIT_ID_CACHE)
-        addi    r8,r8,4
-        bdnz    3b
-        sync                    /* additional sync needed on g4 */
-        isync
-        b       1b
 
 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_PPC_MAPLE)
 /*