diff options
author | David Gibson <david@gibson.dropbear.id.au> | 2006-01-12 22:56:25 -0500 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2006-01-13 05:16:23 -0500 |
commit | e58c3495e6007af59382540bb21ee941e470d88d (patch) | |
tree | 24b559cb768bfa5cf4bdef69f2943b081a1f5afa /arch/powerpc/kernel/misc_32.S | |
parent | 7e78e5e502d4f220d24c6f738f2fdb078ad33607 (diff) |
[PATCH] powerpc: Cleanup LOADADDR etc. asm macros
This patch consolidates the variety of macros used for loading 32 or
64-bit constants in assembler (LOADADDR, LOADBASE, SET_REG_TO_*). The
idea is to make the set of macros consistent across 32 and 64 bit and
to make it more obvious which is the appropriate one to use in a given
situation. The new macros and their semantics are described in the
comments in ppc_asm.h.
In the process, we change several places that were unnecessarily using
immediate loads on ppc64 to use the GOT/TOC. Likewise we cleanup a
couple of places where we were clumsily subtracting PAGE_OFFSET with
asm instructions to use assemble-time arithmetic or the toreal() macro
instead.
Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/kernel/misc_32.S')
-rw-r--r-- | arch/powerpc/kernel/misc_32.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index 01d0d97a16e1..be982023409e 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S | |||
@@ -68,7 +68,7 @@ _GLOBAL(reloc_offset) | |||
68 | mflr r0 | 68 | mflr r0 |
69 | bl 1f | 69 | bl 1f |
70 | 1: mflr r3 | 70 | 1: mflr r3 |
71 | LOADADDR(r4,1b) | 71 | LOAD_REG_IMMEDIATE(r4,1b) |
72 | subf r3,r4,r3 | 72 | subf r3,r4,r3 |
73 | mtlr r0 | 73 | mtlr r0 |
74 | blr | 74 | blr |
@@ -80,7 +80,7 @@ _GLOBAL(add_reloc_offset) | |||
80 | mflr r0 | 80 | mflr r0 |
81 | bl 1f | 81 | bl 1f |
82 | 1: mflr r5 | 82 | 1: mflr r5 |
83 | LOADADDR(r4,1b) | 83 | LOAD_REG_IMMEDIATE(r4,1b) |
84 | subf r5,r4,r5 | 84 | subf r5,r4,r5 |
85 | add r3,r3,r5 | 85 | add r3,r3,r5 |
86 | mtlr r0 | 86 | mtlr r0 |