powerpc/44x: Support 16K/64K base page sizes on 44x

This adds support for 16k and 64k page sizes on PowerPC 44x processors.

The PGDIR table is much smaller than a page when using 16k or 64k
pages (512 and 32 bytes respectively) so we allocate the PGDIR with
kzalloc() instead of __get_free_pages().

One PTE table covers rather a large memory area when using 16k or 64k
pages (32MB or 512MB respectively), so we can easily put FIXMAP and
PKMAP in the area covered by one PTE table.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Vladimir Panfilov <pvr@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 6 insertions, 6 deletions

diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index ae0d084b6a24..15f28e0de78d 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -426,8 +426,8 @@ _GLOBAL(__flush_dcache_icache)
 BEGIN_FTR_SECTION
         blr
 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
-        rlwinm  r3,r3,0,0,19                    /* Get page base address */
-        li      r4,4096/L1_CACHE_BYTES  /* Number of lines in a page */
+        rlwinm  r3,r3,0,0,31-PAGE_SHIFT         /* Get page base address */
+        li      r4,PAGE_SIZE/L1_CACHE_BYTES     /* Number of lines in a page */
         mtctr   r4
         mr      r6,r3
 0:      dcbst   0,r3                            /* Write line to ram */
@@ -467,8 +467,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
         rlwinm  r0,r10,0,28,26                  /* clear DR */
         mtmsr   r0
         isync
-        rlwinm  r3,r3,0,0,19                    /* Get page base address */
-        li      r4,4096/L1_CACHE_BYTES  /* Number of lines in a page */
+        rlwinm  r3,r3,0,0,31-PAGE_SHIFT         /* Get page base address */
+        li      r4,PAGE_SIZE/L1_CACHE_BYTES     /* Number of lines in a page */
         mtctr   r4
         mr      r6,r3
 0:      dcbst   0,r3                            /* Write line to ram */
@@ -492,7 +492,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
  * void clear_pages(void *page, int order) ;
  */
 _GLOBAL(clear_pages)
-        li      r0,4096/L1_CACHE_BYTES
+        li      r0,PAGE_SIZE/L1_CACHE_BYTES
         slw     r0,r0,r4
         mtctr   r0
 #ifdef CONFIG_8xx
@@ -550,7 +550,7 @@ _GLOBAL(copy_page)
         dcbt    r5,r4
         li      r11,L1_CACHE_BYTES+4
 #endif /* MAX_COPY_PREFETCH */
-        li      r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH
+        li      r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
         crclr   4*cr0+eq
 2:
         mtctr   r0