diff options
| author | Stephen Rothwell <sfr@canb.auug.org.au> | 2006-09-19 08:17:49 -0400 |
|---|---|---|
| committer | Stephen Rothwell <sfr@canb.auug.org.au> | 2006-09-20 00:06:18 -0400 |
| commit | 5adcaf50cf697aa4d0c731107003c1383b59b214 (patch) | |
| tree | c4f93c02f43c325066a46e9d9221cac9d51125d8 /arch/powerpc/kernel/misc.S | |
| parent | 73ea9e1bcb8eea4f3b2052fe7ccd7ee4b5a271a0 (diff) | |
[POWERPC] convert string i/o operations to C
This produces essentially the same code and will make the iSeries i/o
consolidation easier.
The count parameter is changed to long since that will produce the same
(better) code on 32 and 64 bit builds.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Diffstat (limited to 'arch/powerpc/kernel/misc.S')
| -rw-r--r-- | arch/powerpc/kernel/misc.S | 95 |
1 files changed, 0 insertions, 95 deletions
diff --git a/arch/powerpc/kernel/misc.S b/arch/powerpc/kernel/misc.S index 6feb391422ec..330c9dc7db86 100644 --- a/arch/powerpc/kernel/misc.S +++ b/arch/powerpc/kernel/misc.S | |||
| @@ -43,98 +43,3 @@ _GLOBAL(add_reloc_offset) | |||
| 43 | add r3,r3,r5 | 43 | add r3,r3,r5 |
| 44 | mtlr r0 | 44 | mtlr r0 |
| 45 | blr | 45 | blr |
| 46 | |||
| 47 | /* | ||
| 48 | * I/O string operations | ||
| 49 | * | ||
| 50 | * insb(port, buf, len) | ||
| 51 | * outsb(port, buf, len) | ||
| 52 | * insw(port, buf, len) | ||
| 53 | * outsw(port, buf, len) | ||
| 54 | * insl(port, buf, len) | ||
| 55 | * outsl(port, buf, len) | ||
| 56 | * insw_ns(port, buf, len) | ||
| 57 | * outsw_ns(port, buf, len) | ||
| 58 | * insl_ns(port, buf, len) | ||
| 59 | * outsl_ns(port, buf, len) | ||
| 60 | * | ||
| 61 | * The *_ns versions don't do byte-swapping. | ||
| 62 | */ | ||
| 63 | _GLOBAL(_insb) | ||
| 64 | sync | ||
| 65 | cmpwi 0,r5,0 | ||
| 66 | mtctr r5 | ||
| 67 | subi r4,r4,1 | ||
| 68 | blelr- | ||
| 69 | 00: lbz r5,0(r3) | ||
| 70 | eieio | ||
| 71 | stbu r5,1(r4) | ||
| 72 | bdnz 00b | ||
| 73 | twi 0,r5,0 | ||
| 74 | isync | ||
| 75 | blr | ||
| 76 | |||
| 77 | _GLOBAL(_outsb) | ||
| 78 | cmpwi 0,r5,0 | ||
| 79 | mtctr r5 | ||
| 80 | subi r4,r4,1 | ||
| 81 | blelr- | ||
| 82 | sync | ||
| 83 | 00: lbzu r5,1(r4) | ||
| 84 | stb r5,0(r3) | ||
| 85 | bdnz 00b | ||
| 86 | sync | ||
| 87 | blr | ||
| 88 | |||
| 89 | _GLOBAL(_insw_ns) | ||
| 90 | sync | ||
| 91 | cmpwi 0,r5,0 | ||
| 92 | mtctr r5 | ||
| 93 | subi r4,r4,2 | ||
| 94 | blelr- | ||
| 95 | 00: lhz r5,0(r3) | ||
| 96 | eieio | ||
| 97 | sthu r5,2(r4) | ||
| 98 | bdnz 00b | ||
| 99 | twi 0,r5,0 | ||
| 100 | isync | ||
| 101 | blr | ||
| 102 | |||
| 103 | _GLOBAL(_outsw_ns) | ||
| 104 | cmpwi 0,r5,0 | ||
| 105 | mtctr r5 | ||
| 106 | subi r4,r4,2 | ||
| 107 | blelr- | ||
| 108 | sync | ||
| 109 | 00: lhzu r5,2(r4) | ||
| 110 | sth r5,0(r3) | ||
| 111 | bdnz 00b | ||
| 112 | sync | ||
| 113 | blr | ||
| 114 | |||
| 115 | _GLOBAL(_insl_ns) | ||
| 116 | sync | ||
| 117 | cmpwi 0,r5,0 | ||
| 118 | mtctr r5 | ||
| 119 | subi r4,r4,4 | ||
| 120 | blelr- | ||
| 121 | 00: lwz r5,0(r3) | ||
| 122 | eieio | ||
| 123 | stwu r5,4(r4) | ||
| 124 | bdnz 00b | ||
| 125 | twi 0,r5,0 | ||
| 126 | isync | ||
| 127 | blr | ||
| 128 | |||
| 129 | _GLOBAL(_outsl_ns) | ||
| 130 | cmpwi 0,r5,0 | ||
| 131 | mtctr r5 | ||
| 132 | subi r4,r4,4 | ||
| 133 | blelr- | ||
| 134 | sync | ||
| 135 | 00: lwzu r5,4(r4) | ||
| 136 | stw r5,0(r3) | ||
| 137 | bdnz 00b | ||
| 138 | sync | ||
| 139 | blr | ||
| 140 | |||