powerpc/e500mc: flush L2 on NAP for e500mc

If we have an L2CSR register (e500mc) we need to flush the L2 before going
to nap.  We use the HW flush mechanism provided in that register.

The code reuses the CPU_FTR_604_PERF_MON bit as it is no longer used by
any code in the kernel.  Additionally we didn't reuse the exist L2CR
feature bit as this is intended for the 7xxx L2CR register and L2CSR
is part of the new Freescale "Book-E" registers.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 9 insertions, 0 deletions

diff --git a/arch/powerpc/kernel/idle_e500.S b/arch/powerpc/kernel/idle_e500.S
index 267adec2491b..06304034b393 100644
--- a/arch/powerpc/kernel/idle_e500.S
+++ b/arch/powerpc/kernel/idle_e500.S
@@ -47,6 +47,15 @@ BEGIN_FTR_SECTION
         mtlr    r0
         lis     r3,HID0_NAP@h
 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
+BEGIN_FTR_SECTION
+        msync
+        li      r7,L2CSR0_L2FL@l
+        mtspr   SPRN_L2CSR0,r7
+2:
+        mfspr   r7,SPRN_L2CSR0
+        andi.   r4,r7,L2CSR0_L2FL@l
+        bne     2b
+END_FTR_SECTION_IFSET(CPU_FTR_L2CSR|CPU_FTR_CAN_NAP)
 1:
         /* Go to NAP or DOZE now */
         mfspr   r4,SPRN_HID0