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authorKumar Gala <galak@kernel.crashing.org>2009-01-08 09:31:20 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-01-28 19:16:50 -0500
commit105c31df6fc5a424b480321763b5598cf3817821 (patch)
treeda2bee2ae3db6b0af900947f60cb0c7bf1b9bd1f /arch/powerpc/kernel/head_fsl_booke.S
parent0585a155a7318e69d43ef20636c2f072ad17d03f (diff)
powerpc/fsl-booke: Cleanup init/exception setup to be runtime
We currently have a few variants of fsl-booke processors (e500v1, e500v2, e500mc, and e200). They all have minor differences that we had previously been handling via ifdefs. To move towards having this support the following changes have been made: * PID1, PID2 only exist on e500v1 & e500v2 and should not be accessed on e500mc or e200. We use MMUCFG[NPIDS] to determine which case we are since we only touch PID1/2 in extremely early init code. * Not all IVORs exist on all the processors so introduce cpu_setup functions for each variant to setup the proper IVORs that are either unique or exist but have some variations between the processors Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel/head_fsl_booke.S')
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S81
1 files changed, 54 insertions, 27 deletions
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 36ffb3504a4f..64ecb1603a77 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -103,10 +103,15 @@ invstr: mflr r6 /* Make it accessible */
103 or r7,r7,r4 103 or r7,r7,r4
104 mtspr SPRN_MAS6,r7 104 mtspr SPRN_MAS6,r7
105 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */ 105 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
106#ifndef CONFIG_E200
107 mfspr r7,SPRN_MAS1 106 mfspr r7,SPRN_MAS1
108 andis. r7,r7,MAS1_VALID@h 107 andis. r7,r7,MAS1_VALID@h
109 bne match_TLB 108 bne match_TLB
109
110 mfspr r7,SPRN_MMUCFG
111 rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
112 cmpwi r7,3
113 bne match_TLB /* skip if NPIDS != 3 */
114
110 mfspr r7,SPRN_PID1 115 mfspr r7,SPRN_PID1
111 slwi r7,r7,16 116 slwi r7,r7,16
112 or r7,r7,r4 117 or r7,r7,r4
@@ -120,7 +125,7 @@ invstr: mflr r6 /* Make it accessible */
120 or r7,r7,r4 125 or r7,r7,r4
121 mtspr SPRN_MAS6,r7 126 mtspr SPRN_MAS6,r7
122 tlbsx 0,r6 /* Fall through, we had to match */ 127 tlbsx 0,r6 /* Fall through, we had to match */
123#endif 128
124match_TLB: 129match_TLB:
125 mfspr r7,SPRN_MAS0 130 mfspr r7,SPRN_MAS0
126 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */ 131 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
@@ -215,14 +220,19 @@ skpinv: addi r6,r6,1 /* Increment */
215 220
216/* 4. Clear out PIDs & Search info */ 221/* 4. Clear out PIDs & Search info */
217 li r6,0 222 li r6,0
223 mtspr SPRN_MAS6,r6
218 mtspr SPRN_PID0,r6 224 mtspr SPRN_PID0,r6
219#ifndef CONFIG_E200 225
226 mfspr r7,SPRN_MMUCFG
227 rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
228 cmpwi r7,3
229 bne 2f /* skip if NPIDS != 3 */
230
220 mtspr SPRN_PID1,r6 231 mtspr SPRN_PID1,r6
221 mtspr SPRN_PID2,r6 232 mtspr SPRN_PID2,r6
222#endif
223 mtspr SPRN_MAS6,r6
224 233
225/* 5. Invalidate mapping we started in */ 234/* 5. Invalidate mapping we started in */
2352:
226 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */ 236 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
227 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */ 237 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
228 mtspr SPRN_MAS0,r7 238 mtspr SPRN_MAS0,r7
@@ -298,19 +308,7 @@ skpinv: addi r6,r6,1 /* Increment */
298 SET_IVOR(12, WatchdogTimer); 308 SET_IVOR(12, WatchdogTimer);
299 SET_IVOR(13, DataTLBError); 309 SET_IVOR(13, DataTLBError);
300 SET_IVOR(14, InstructionTLBError); 310 SET_IVOR(14, InstructionTLBError);
301 SET_IVOR(15, DebugDebug);
302#if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
303 SET_IVOR(15, DebugCrit); 311 SET_IVOR(15, DebugCrit);
304#endif
305 SET_IVOR(32, SPEUnavailable);
306 SET_IVOR(33, SPEFloatingPointData);
307 SET_IVOR(34, SPEFloatingPointRound);
308#ifndef CONFIG_E200
309 SET_IVOR(35, PerformanceMonitor);
310#endif
311#ifdef CONFIG_PPC_E500MC
312 SET_IVOR(36, Doorbell);
313#endif
314 312
315 /* Establish the interrupt vector base */ 313 /* Establish the interrupt vector base */
316 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ 314 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
@@ -329,12 +327,6 @@ skpinv: addi r6,r6,1 /* Increment */
329 oris r2,r2,HID0_DOZE@h 327 oris r2,r2,HID0_DOZE@h
330 mtspr SPRN_HID0, r2 328 mtspr SPRN_HID0, r2
331#endif 329#endif
332#ifdef CONFIG_E200
333 /* enable dedicated debug exception handling resources (Debug APU) */
334 mfspr r2,SPRN_HID0
335 ori r2,r2,HID0_DAPUEN@l
336 mtspr SPRN_HID0,r2
337#endif
338 330
339#if !defined(CONFIG_BDI_SWITCH) 331#if !defined(CONFIG_BDI_SWITCH)
340 /* 332 /*
@@ -706,15 +698,11 @@ interrupt_base:
706 /* Performance Monitor */ 698 /* Performance Monitor */
707 EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD) 699 EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
708 700
709#ifdef CONFIG_PPC_E500MC
710 EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_STD) 701 EXCEPTION(0x2070, Doorbell, unknown_exception, EXC_XFER_STD)
711#endif
712 702
713 /* Debug Interrupt */ 703 /* Debug Interrupt */
714 DEBUG_DEBUG_EXCEPTION 704 DEBUG_DEBUG_EXCEPTION
715#if defined(CONFIG_E500) && !defined(CONFIG_PPC_E500MC)
716 DEBUG_CRIT_EXCEPTION 705 DEBUG_CRIT_EXCEPTION
717#endif
718 706
719/* 707/*
720 * Local functions 708 * Local functions
@@ -897,6 +885,45 @@ KernelSPE:
897 * Global functions 885 * Global functions
898 */ 886 */
899 887
888/* Adjust or setup IVORs for e200 */
889_GLOBAL(__setup_e200_ivors)
890 li r3,DebugDebug@l
891 mtspr SPRN_IVOR15,r3
892 li r3,SPEUnavailable@l
893 mtspr SPRN_IVOR32,r3
894 li r3,SPEFloatingPointData@l
895 mtspr SPRN_IVOR33,r3
896 li r3,SPEFloatingPointRound@l
897 mtspr SPRN_IVOR34,r3
898 sync
899 blr
900
901/* Adjust or setup IVORs for e500v1/v2 */
902_GLOBAL(__setup_e500_ivors)
903 li r3,DebugCrit@l
904 mtspr SPRN_IVOR15,r3
905 li r3,SPEUnavailable@l
906 mtspr SPRN_IVOR32,r3
907 li r3,SPEFloatingPointData@l
908 mtspr SPRN_IVOR33,r3
909 li r3,SPEFloatingPointRound@l
910 mtspr SPRN_IVOR34,r3
911 li r3,PerformanceMonitor@l
912 mtspr SPRN_IVOR35,r3
913 sync
914 blr
915
916/* Adjust or setup IVORs for e500mc */
917_GLOBAL(__setup_e500mc_ivors)
918 li r3,DebugDebug@l
919 mtspr SPRN_IVOR15,r3
920 li r3,PerformanceMonitor@l
921 mtspr SPRN_IVOR35,r3
922 li r3,Doorbell@l
923 mtspr SPRN_IVOR36,r3
924 sync
925 blr
926
900/* 927/*
901 * extern void loadcam_entry(unsigned int index) 928 * extern void loadcam_entry(unsigned int index)
902 * 929 *