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authorRoland McGrath <roland@redhat.com>2009-05-28 17:26:38 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-06-08 23:29:25 -0400
commitec097c84dff17511f2693e6ef6c3064dfbf0a3af (patch)
tree3eac516a13730dcb371c094c0e8d35c9768c9c23 /arch/powerpc/kernel/head_booke.h
parentdac4ccfb64bcdd5b4c248ccc22903d67486573cd (diff)
powerpc: Add PTRACE_SINGLEBLOCK support
Reworked by: Benjamin Herrenschmidt <benh@kernel.crashing.org> This adds block-step support on powerpc, including a PTRACE_SINGLEBLOCK request for ptrace. The BookE implementation is tweaked to fire a single step after a block step in order to mimmic the server behaviour. Signed-off-by: Roland McGrath <roland@redhat.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel/head_booke.h')
-rw-r--r--arch/powerpc/kernel/head_booke.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index 95f39f1e68d4..5f9febc8d143 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -256,7 +256,7 @@ label:
256 * off DE in the DSRR1 value and clearing the debug status. \ 256 * off DE in the DSRR1 value and clearing the debug status. \
257 */ \ 257 */ \
258 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ 258 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
259 andis. r10,r10,DBSR_IC@h; \ 259 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
260 beq+ 2f; \ 260 beq+ 2f; \
261 \ 261 \
262 lis r10,KERNELBASE@h; /* check if exception in vectors */ \ 262 lis r10,KERNELBASE@h; /* check if exception in vectors */ \
@@ -271,7 +271,7 @@ label:
271 \ 271 \
272 /* here it looks like we got an inappropriate debug exception. */ \ 272 /* here it looks like we got an inappropriate debug exception. */ \
2731: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \ 2731: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \
274 lis r10,DBSR_IC@h; /* clear the IC event */ \ 274 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
275 mtspr SPRN_DBSR,r10; \ 275 mtspr SPRN_DBSR,r10; \
276 /* restore state and get out */ \ 276 /* restore state and get out */ \
277 lwz r10,_CCR(r11); \ 277 lwz r10,_CCR(r11); \
@@ -309,7 +309,7 @@ label:
309 * off DE in the CSRR1 value and clearing the debug status. \ 309 * off DE in the CSRR1 value and clearing the debug status. \
310 */ \ 310 */ \
311 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ 311 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
312 andis. r10,r10,DBSR_IC@h; \ 312 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
313 beq+ 2f; \ 313 beq+ 2f; \
314 \ 314 \
315 lis r10,KERNELBASE@h; /* check if exception in vectors */ \ 315 lis r10,KERNELBASE@h; /* check if exception in vectors */ \
@@ -317,14 +317,14 @@ label:
317 cmplw r12,r10; \ 317 cmplw r12,r10; \
318 blt+ 2f; /* addr below exception vectors */ \ 318 blt+ 2f; /* addr below exception vectors */ \
319 \ 319 \
320 lis r10,DebugCrit@h; \ 320 lis r10,DebugCrit@h; \
321 ori r10,r10,DebugCrit@l; \ 321 ori r10,r10,DebugCrit@l; \
322 cmplw r12,r10; \ 322 cmplw r12,r10; \
323 bgt+ 2f; /* addr above exception vectors */ \ 323 bgt+ 2f; /* addr above exception vectors */ \
324 \ 324 \
325 /* here it looks like we got an inappropriate debug exception. */ \ 325 /* here it looks like we got an inappropriate debug exception. */ \
3261: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \ 3261: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \
327 lis r10,DBSR_IC@h; /* clear the IC event */ \ 327 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
328 mtspr SPRN_DBSR,r10; \ 328 mtspr SPRN_DBSR,r10; \
329 /* restore state and get out */ \ 329 /* restore state and get out */ \
330 lwz r10,_CCR(r11); \ 330 lwz r10,_CCR(r11); \