diff options
author | Paul Mackerras <paulus@samba.org> | 2005-10-10 00:01:07 -0400 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2005-10-10 00:01:07 -0400 |
commit | b5bbeb23732196558222a2827092f5b7be8a7945 (patch) | |
tree | d367c3c0c52e9db865c2ceaecc32498a65337c7b /arch/powerpc/kernel/head_64.S | |
parent | 05f62a5c049845eab8dfb3aeda55c18a2d4396e3 (diff) |
powerpc: Use SPRN_xxx rather than xxx for SPR numbers
This changes symbols like HID0, SPRG3, SRR0, SRR1 etc. that refer to
special purpose registers to SPRN_HID0, SPRN_SPRG3, etc. Using the
SPRN_ symbols clutters the namespace less, and the forthcoming merge
of asm/processor.h and asm/reg.h is going to remove the non-SPRN_
versions.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/kernel/head_64.S')
-rw-r--r-- | arch/powerpc/kernel/head_64.S | 196 |
1 files changed, 98 insertions, 98 deletions
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index a36ee6ecbaea..7889ff8473b9 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S | |||
@@ -25,7 +25,7 @@ | |||
25 | 25 | ||
26 | #include <linux/config.h> | 26 | #include <linux/config.h> |
27 | #include <linux/threads.h> | 27 | #include <linux/threads.h> |
28 | #include <asm/processor.h> | 28 | #include <asm/reg.h> |
29 | #include <asm/page.h> | 29 | #include <asm/page.h> |
30 | #include <asm/mmu.h> | 30 | #include <asm/mmu.h> |
31 | #include <asm/systemcfg.h> | 31 | #include <asm/systemcfg.h> |
@@ -201,22 +201,22 @@ exception_marker: | |||
201 | #define EX_CCR 60 | 201 | #define EX_CCR 60 |
202 | 202 | ||
203 | #define EXCEPTION_PROLOG_PSERIES(area, label) \ | 203 | #define EXCEPTION_PROLOG_PSERIES(area, label) \ |
204 | mfspr r13,SPRG3; /* get paca address into r13 */ \ | 204 | mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ |
205 | std r9,area+EX_R9(r13); /* save r9 - r12 */ \ | 205 | std r9,area+EX_R9(r13); /* save r9 - r12 */ \ |
206 | std r10,area+EX_R10(r13); \ | 206 | std r10,area+EX_R10(r13); \ |
207 | std r11,area+EX_R11(r13); \ | 207 | std r11,area+EX_R11(r13); \ |
208 | std r12,area+EX_R12(r13); \ | 208 | std r12,area+EX_R12(r13); \ |
209 | mfspr r9,SPRG1; \ | 209 | mfspr r9,SPRN_SPRG1; \ |
210 | std r9,area+EX_R13(r13); \ | 210 | std r9,area+EX_R13(r13); \ |
211 | mfcr r9; \ | 211 | mfcr r9; \ |
212 | clrrdi r12,r13,32; /* get high part of &label */ \ | 212 | clrrdi r12,r13,32; /* get high part of &label */ \ |
213 | mfmsr r10; \ | 213 | mfmsr r10; \ |
214 | mfspr r11,SRR0; /* save SRR0 */ \ | 214 | mfspr r11,SPRN_SRR0; /* save SRR0 */ \ |
215 | ori r12,r12,(label)@l; /* virt addr of handler */ \ | 215 | ori r12,r12,(label)@l; /* virt addr of handler */ \ |
216 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ | 216 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \ |
217 | mtspr SRR0,r12; \ | 217 | mtspr SPRN_SRR0,r12; \ |
218 | mfspr r12,SRR1; /* and SRR1 */ \ | 218 | mfspr r12,SPRN_SRR1; /* and SRR1 */ \ |
219 | mtspr SRR1,r10; \ | 219 | mtspr SPRN_SRR1,r10; \ |
220 | rfid; \ | 220 | rfid; \ |
221 | b . /* prevent speculative execution */ | 221 | b . /* prevent speculative execution */ |
222 | 222 | ||
@@ -225,12 +225,12 @@ exception_marker: | |||
225 | * This code runs with relocation on. | 225 | * This code runs with relocation on. |
226 | */ | 226 | */ |
227 | #define EXCEPTION_PROLOG_ISERIES_1(area) \ | 227 | #define EXCEPTION_PROLOG_ISERIES_1(area) \ |
228 | mfspr r13,SPRG3; /* get paca address into r13 */ \ | 228 | mfspr r13,SPRN_SPRG3; /* get paca address into r13 */ \ |
229 | std r9,area+EX_R9(r13); /* save r9 - r12 */ \ | 229 | std r9,area+EX_R9(r13); /* save r9 - r12 */ \ |
230 | std r10,area+EX_R10(r13); \ | 230 | std r10,area+EX_R10(r13); \ |
231 | std r11,area+EX_R11(r13); \ | 231 | std r11,area+EX_R11(r13); \ |
232 | std r12,area+EX_R12(r13); \ | 232 | std r12,area+EX_R12(r13); \ |
233 | mfspr r9,SPRG1; \ | 233 | mfspr r9,SPRN_SPRG1; \ |
234 | std r9,area+EX_R13(r13); \ | 234 | std r9,area+EX_R13(r13); \ |
235 | mfcr r9 | 235 | mfcr r9 |
236 | 236 | ||
@@ -283,7 +283,7 @@ exception_marker: | |||
283 | std r9,_LINK(r1); \ | 283 | std r9,_LINK(r1); \ |
284 | mfctr r10; /* save CTR in stackframe */ \ | 284 | mfctr r10; /* save CTR in stackframe */ \ |
285 | std r10,_CTR(r1); \ | 285 | std r10,_CTR(r1); \ |
286 | mfspr r11,XER; /* save XER in stackframe */ \ | 286 | mfspr r11,SPRN_XER; /* save XER in stackframe */ \ |
287 | std r11,_XER(r1); \ | 287 | std r11,_XER(r1); \ |
288 | li r9,(n)+1; \ | 288 | li r9,(n)+1; \ |
289 | std r9,_TRAP(r1); /* set trap number */ \ | 289 | std r9,_TRAP(r1); /* set trap number */ \ |
@@ -300,7 +300,7 @@ exception_marker: | |||
300 | .globl label##_pSeries; \ | 300 | .globl label##_pSeries; \ |
301 | label##_pSeries: \ | 301 | label##_pSeries: \ |
302 | HMT_MEDIUM; \ | 302 | HMT_MEDIUM; \ |
303 | mtspr SPRG1,r13; /* save r13 */ \ | 303 | mtspr SPRN_SPRG1,r13; /* save r13 */ \ |
304 | RUNLATCH_ON(r13); \ | 304 | RUNLATCH_ON(r13); \ |
305 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) | 305 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common) |
306 | 306 | ||
@@ -308,7 +308,7 @@ label##_pSeries: \ | |||
308 | .globl label##_iSeries; \ | 308 | .globl label##_iSeries; \ |
309 | label##_iSeries: \ | 309 | label##_iSeries: \ |
310 | HMT_MEDIUM; \ | 310 | HMT_MEDIUM; \ |
311 | mtspr SPRG1,r13; /* save r13 */ \ | 311 | mtspr SPRN_SPRG1,r13; /* save r13 */ \ |
312 | RUNLATCH_ON(r13); \ | 312 | RUNLATCH_ON(r13); \ |
313 | EXCEPTION_PROLOG_ISERIES_1(area); \ | 313 | EXCEPTION_PROLOG_ISERIES_1(area); \ |
314 | EXCEPTION_PROLOG_ISERIES_2; \ | 314 | EXCEPTION_PROLOG_ISERIES_2; \ |
@@ -318,7 +318,7 @@ label##_iSeries: \ | |||
318 | .globl label##_iSeries; \ | 318 | .globl label##_iSeries; \ |
319 | label##_iSeries: \ | 319 | label##_iSeries: \ |
320 | HMT_MEDIUM; \ | 320 | HMT_MEDIUM; \ |
321 | mtspr SPRG1,r13; /* save r13 */ \ | 321 | mtspr SPRN_SPRG1,r13; /* save r13 */ \ |
322 | RUNLATCH_ON(r13); \ | 322 | RUNLATCH_ON(r13); \ |
323 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \ | 323 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \ |
324 | lbz r10,PACAPROCENABLED(r13); \ | 324 | lbz r10,PACAPROCENABLED(r13); \ |
@@ -388,7 +388,7 @@ __start_interrupts: | |||
388 | . = 0x200 | 388 | . = 0x200 |
389 | _machine_check_pSeries: | 389 | _machine_check_pSeries: |
390 | HMT_MEDIUM | 390 | HMT_MEDIUM |
391 | mtspr SPRG1,r13 /* save r13 */ | 391 | mtspr SPRN_SPRG1,r13 /* save r13 */ |
392 | RUNLATCH_ON(r13) | 392 | RUNLATCH_ON(r13) |
393 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) | 393 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) |
394 | 394 | ||
@@ -396,18 +396,18 @@ _machine_check_pSeries: | |||
396 | .globl data_access_pSeries | 396 | .globl data_access_pSeries |
397 | data_access_pSeries: | 397 | data_access_pSeries: |
398 | HMT_MEDIUM | 398 | HMT_MEDIUM |
399 | mtspr SPRG1,r13 | 399 | mtspr SPRN_SPRG1,r13 |
400 | BEGIN_FTR_SECTION | 400 | BEGIN_FTR_SECTION |
401 | mtspr SPRG2,r12 | 401 | mtspr SPRN_SPRG2,r12 |
402 | mfspr r13,DAR | 402 | mfspr r13,SPRN_DAR |
403 | mfspr r12,DSISR | 403 | mfspr r12,SPRN_DSISR |
404 | srdi r13,r13,60 | 404 | srdi r13,r13,60 |
405 | rlwimi r13,r12,16,0x20 | 405 | rlwimi r13,r12,16,0x20 |
406 | mfcr r12 | 406 | mfcr r12 |
407 | cmpwi r13,0x2c | 407 | cmpwi r13,0x2c |
408 | beq .do_stab_bolted_pSeries | 408 | beq .do_stab_bolted_pSeries |
409 | mtcrf 0x80,r12 | 409 | mtcrf 0x80,r12 |
410 | mfspr r12,SPRG2 | 410 | mfspr r12,SPRN_SPRG2 |
411 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) | 411 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) |
412 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) | 412 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) |
413 | 413 | ||
@@ -415,19 +415,19 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SLB) | |||
415 | .globl data_access_slb_pSeries | 415 | .globl data_access_slb_pSeries |
416 | data_access_slb_pSeries: | 416 | data_access_slb_pSeries: |
417 | HMT_MEDIUM | 417 | HMT_MEDIUM |
418 | mtspr SPRG1,r13 | 418 | mtspr SPRN_SPRG1,r13 |
419 | RUNLATCH_ON(r13) | 419 | RUNLATCH_ON(r13) |
420 | mfspr r13,SPRG3 /* get paca address into r13 */ | 420 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
421 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ | 421 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ |
422 | std r10,PACA_EXSLB+EX_R10(r13) | 422 | std r10,PACA_EXSLB+EX_R10(r13) |
423 | std r11,PACA_EXSLB+EX_R11(r13) | 423 | std r11,PACA_EXSLB+EX_R11(r13) |
424 | std r12,PACA_EXSLB+EX_R12(r13) | 424 | std r12,PACA_EXSLB+EX_R12(r13) |
425 | std r3,PACA_EXSLB+EX_R3(r13) | 425 | std r3,PACA_EXSLB+EX_R3(r13) |
426 | mfspr r9,SPRG1 | 426 | mfspr r9,SPRN_SPRG1 |
427 | std r9,PACA_EXSLB+EX_R13(r13) | 427 | std r9,PACA_EXSLB+EX_R13(r13) |
428 | mfcr r9 | 428 | mfcr r9 |
429 | mfspr r12,SRR1 /* and SRR1 */ | 429 | mfspr r12,SPRN_SRR1 /* and SRR1 */ |
430 | mfspr r3,DAR | 430 | mfspr r3,SPRN_DAR |
431 | b .do_slb_miss /* Rel. branch works in real mode */ | 431 | b .do_slb_miss /* Rel. branch works in real mode */ |
432 | 432 | ||
433 | STD_EXCEPTION_PSERIES(0x400, instruction_access) | 433 | STD_EXCEPTION_PSERIES(0x400, instruction_access) |
@@ -436,19 +436,19 @@ data_access_slb_pSeries: | |||
436 | .globl instruction_access_slb_pSeries | 436 | .globl instruction_access_slb_pSeries |
437 | instruction_access_slb_pSeries: | 437 | instruction_access_slb_pSeries: |
438 | HMT_MEDIUM | 438 | HMT_MEDIUM |
439 | mtspr SPRG1,r13 | 439 | mtspr SPRN_SPRG1,r13 |
440 | RUNLATCH_ON(r13) | 440 | RUNLATCH_ON(r13) |
441 | mfspr r13,SPRG3 /* get paca address into r13 */ | 441 | mfspr r13,SPRN_SPRG3 /* get paca address into r13 */ |
442 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ | 442 | std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */ |
443 | std r10,PACA_EXSLB+EX_R10(r13) | 443 | std r10,PACA_EXSLB+EX_R10(r13) |
444 | std r11,PACA_EXSLB+EX_R11(r13) | 444 | std r11,PACA_EXSLB+EX_R11(r13) |
445 | std r12,PACA_EXSLB+EX_R12(r13) | 445 | std r12,PACA_EXSLB+EX_R12(r13) |
446 | std r3,PACA_EXSLB+EX_R3(r13) | 446 | std r3,PACA_EXSLB+EX_R3(r13) |
447 | mfspr r9,SPRG1 | 447 | mfspr r9,SPRN_SPRG1 |
448 | std r9,PACA_EXSLB+EX_R13(r13) | 448 | std r9,PACA_EXSLB+EX_R13(r13) |
449 | mfcr r9 | 449 | mfcr r9 |
450 | mfspr r12,SRR1 /* and SRR1 */ | 450 | mfspr r12,SPRN_SRR1 /* and SRR1 */ |
451 | mfspr r3,SRR0 /* SRR0 is faulting address */ | 451 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ |
452 | b .do_slb_miss /* Rel. branch works in real mode */ | 452 | b .do_slb_miss /* Rel. branch works in real mode */ |
453 | 453 | ||
454 | STD_EXCEPTION_PSERIES(0x500, hardware_interrupt) | 454 | STD_EXCEPTION_PSERIES(0x500, hardware_interrupt) |
@@ -466,15 +466,15 @@ system_call_pSeries: | |||
466 | RUNLATCH_ON(r9) | 466 | RUNLATCH_ON(r9) |
467 | mr r9,r13 | 467 | mr r9,r13 |
468 | mfmsr r10 | 468 | mfmsr r10 |
469 | mfspr r13,SPRG3 | 469 | mfspr r13,SPRN_SPRG3 |
470 | mfspr r11,SRR0 | 470 | mfspr r11,SPRN_SRR0 |
471 | clrrdi r12,r13,32 | 471 | clrrdi r12,r13,32 |
472 | oris r12,r12,system_call_common@h | 472 | oris r12,r12,system_call_common@h |
473 | ori r12,r12,system_call_common@l | 473 | ori r12,r12,system_call_common@l |
474 | mtspr SRR0,r12 | 474 | mtspr SPRN_SRR0,r12 |
475 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI | 475 | ori r10,r10,MSR_IR|MSR_DR|MSR_RI |
476 | mfspr r12,SRR1 | 476 | mfspr r12,SPRN_SRR1 |
477 | mtspr SRR1,r10 | 477 | mtspr SPRN_SRR1,r10 |
478 | rfid | 478 | rfid |
479 | b . /* prevent speculative execution */ | 479 | b . /* prevent speculative execution */ |
480 | 480 | ||
@@ -504,25 +504,25 @@ system_call_pSeries: | |||
504 | .align 7 | 504 | .align 7 |
505 | _GLOBAL(do_stab_bolted_pSeries) | 505 | _GLOBAL(do_stab_bolted_pSeries) |
506 | mtcrf 0x80,r12 | 506 | mtcrf 0x80,r12 |
507 | mfspr r12,SPRG2 | 507 | mfspr r12,SPRN_SPRG2 |
508 | EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) | 508 | EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) |
509 | 509 | ||
510 | /* | 510 | /* |
511 | * Vectors for the FWNMI option. Share common code. | 511 | * Vectors for the FWNMI option. Share common code. |
512 | */ | 512 | */ |
513 | .globl system_reset_fwnmi | 513 | .globl system_reset_fwnmi |
514 | system_reset_fwnmi: | 514 | system_reset_fwnmi: |
515 | HMT_MEDIUM | 515 | HMT_MEDIUM |
516 | mtspr SPRG1,r13 /* save r13 */ | 516 | mtspr SPRN_SPRG1,r13 /* save r13 */ |
517 | RUNLATCH_ON(r13) | 517 | RUNLATCH_ON(r13) |
518 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common) | 518 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common) |
519 | 519 | ||
520 | .globl machine_check_fwnmi | 520 | .globl machine_check_fwnmi |
521 | machine_check_fwnmi: | 521 | machine_check_fwnmi: |
522 | HMT_MEDIUM | 522 | HMT_MEDIUM |
523 | mtspr SPRG1,r13 /* save r13 */ | 523 | mtspr SPRN_SPRG1,r13 /* save r13 */ |
524 | RUNLATCH_ON(r13) | 524 | RUNLATCH_ON(r13) |
525 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) | 525 | EXCEPTION_PROLOG_PSERIES(PACA_EXMC, machine_check_common) |
526 | 526 | ||
527 | #ifdef CONFIG_PPC_ISERIES | 527 | #ifdef CONFIG_PPC_ISERIES |
528 | /*** ISeries-LPAR interrupt handlers ***/ | 528 | /*** ISeries-LPAR interrupt handlers ***/ |
@@ -531,18 +531,18 @@ machine_check_fwnmi: | |||
531 | 531 | ||
532 | .globl data_access_iSeries | 532 | .globl data_access_iSeries |
533 | data_access_iSeries: | 533 | data_access_iSeries: |
534 | mtspr SPRG1,r13 | 534 | mtspr SPRN_SPRG1,r13 |
535 | BEGIN_FTR_SECTION | 535 | BEGIN_FTR_SECTION |
536 | mtspr SPRG2,r12 | 536 | mtspr SPRN_SPRG2,r12 |
537 | mfspr r13,DAR | 537 | mfspr r13,SPRN_DAR |
538 | mfspr r12,DSISR | 538 | mfspr r12,SPRN_DSISR |
539 | srdi r13,r13,60 | 539 | srdi r13,r13,60 |
540 | rlwimi r13,r12,16,0x20 | 540 | rlwimi r13,r12,16,0x20 |
541 | mfcr r12 | 541 | mfcr r12 |
542 | cmpwi r13,0x2c | 542 | cmpwi r13,0x2c |
543 | beq .do_stab_bolted_iSeries | 543 | beq .do_stab_bolted_iSeries |
544 | mtcrf 0x80,r12 | 544 | mtcrf 0x80,r12 |
545 | mfspr r12,SPRG2 | 545 | mfspr r12,SPRN_SPRG2 |
546 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) | 546 | END_FTR_SECTION_IFCLR(CPU_FTR_SLB) |
547 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN) | 547 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN) |
548 | EXCEPTION_PROLOG_ISERIES_2 | 548 | EXCEPTION_PROLOG_ISERIES_2 |
@@ -550,25 +550,25 @@ END_FTR_SECTION_IFCLR(CPU_FTR_SLB) | |||
550 | 550 | ||
551 | .do_stab_bolted_iSeries: | 551 | .do_stab_bolted_iSeries: |
552 | mtcrf 0x80,r12 | 552 | mtcrf 0x80,r12 |
553 | mfspr r12,SPRG2 | 553 | mfspr r12,SPRN_SPRG2 |
554 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) | 554 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) |
555 | EXCEPTION_PROLOG_ISERIES_2 | 555 | EXCEPTION_PROLOG_ISERIES_2 |
556 | b .do_stab_bolted | 556 | b .do_stab_bolted |
557 | 557 | ||
558 | .globl data_access_slb_iSeries | 558 | .globl data_access_slb_iSeries |
559 | data_access_slb_iSeries: | 559 | data_access_slb_iSeries: |
560 | mtspr SPRG1,r13 /* save r13 */ | 560 | mtspr SPRN_SPRG1,r13 /* save r13 */ |
561 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) | 561 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) |
562 | std r3,PACA_EXSLB+EX_R3(r13) | 562 | std r3,PACA_EXSLB+EX_R3(r13) |
563 | ld r12,PACALPPACA+LPPACASRR1(r13) | 563 | ld r12,PACALPPACA+LPPACASRR1(r13) |
564 | mfspr r3,DAR | 564 | mfspr r3,SPRN_DAR |
565 | b .do_slb_miss | 565 | b .do_slb_miss |
566 | 566 | ||
567 | STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN) | 567 | STD_EXCEPTION_ISERIES(0x400, instruction_access, PACA_EXGEN) |
568 | 568 | ||
569 | .globl instruction_access_slb_iSeries | 569 | .globl instruction_access_slb_iSeries |
570 | instruction_access_slb_iSeries: | 570 | instruction_access_slb_iSeries: |
571 | mtspr SPRG1,r13 /* save r13 */ | 571 | mtspr SPRN_SPRG1,r13 /* save r13 */ |
572 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) | 572 | EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB) |
573 | std r3,PACA_EXSLB+EX_R3(r13) | 573 | std r3,PACA_EXSLB+EX_R3(r13) |
574 | ld r12,PACALPPACA+LPPACASRR1(r13) | 574 | ld r12,PACALPPACA+LPPACASRR1(r13) |
@@ -586,7 +586,7 @@ instruction_access_slb_iSeries: | |||
586 | .globl system_call_iSeries | 586 | .globl system_call_iSeries |
587 | system_call_iSeries: | 587 | system_call_iSeries: |
588 | mr r9,r13 | 588 | mr r9,r13 |
589 | mfspr r13,SPRG3 | 589 | mfspr r13,SPRN_SPRG3 |
590 | EXCEPTION_PROLOG_ISERIES_2 | 590 | EXCEPTION_PROLOG_ISERIES_2 |
591 | b system_call_common | 591 | b system_call_common |
592 | 592 | ||
@@ -596,7 +596,7 @@ system_call_iSeries: | |||
596 | 596 | ||
597 | .globl system_reset_iSeries | 597 | .globl system_reset_iSeries |
598 | system_reset_iSeries: | 598 | system_reset_iSeries: |
599 | mfspr r13,SPRG3 /* Get paca address */ | 599 | mfspr r13,SPRN_SPRG3 /* Get paca address */ |
600 | mfmsr r24 | 600 | mfmsr r24 |
601 | ori r24,r24,MSR_RI | 601 | ori r24,r24,MSR_RI |
602 | mtmsrd r24 /* RI on */ | 602 | mtmsrd r24 /* RI on */ |
@@ -639,7 +639,7 @@ iSeries_secondary_smp_loop: | |||
639 | #endif /* CONFIG_SMP */ | 639 | #endif /* CONFIG_SMP */ |
640 | li r0,-1 /* r0=-1 indicates a Hypervisor call */ | 640 | li r0,-1 /* r0=-1 indicates a Hypervisor call */ |
641 | sc /* Invoke the hypervisor via a system call */ | 641 | sc /* Invoke the hypervisor via a system call */ |
642 | mfspr r13,SPRG3 /* Put r13 back ???? */ | 642 | mfspr r13,SPRN_SPRG3 /* Put r13 back ???? */ |
643 | b 1b /* If SMP not configured, secondaries | 643 | b 1b /* If SMP not configured, secondaries |
644 | * loop forever */ | 644 | * loop forever */ |
645 | 645 | ||
@@ -656,8 +656,8 @@ hardware_interrupt_iSeries_masked: | |||
656 | mtcrf 0x80,r9 /* Restore regs */ | 656 | mtcrf 0x80,r9 /* Restore regs */ |
657 | ld r11,PACALPPACA+LPPACASRR0(r13) | 657 | ld r11,PACALPPACA+LPPACASRR0(r13) |
658 | ld r12,PACALPPACA+LPPACASRR1(r13) | 658 | ld r12,PACALPPACA+LPPACASRR1(r13) |
659 | mtspr SRR0,r11 | 659 | mtspr SPRN_SRR0,r11 |
660 | mtspr SRR1,r12 | 660 | mtspr SPRN_SRR1,r12 |
661 | ld r9,PACA_EXGEN+EX_R9(r13) | 661 | ld r9,PACA_EXGEN+EX_R9(r13) |
662 | ld r10,PACA_EXGEN+EX_R10(r13) | 662 | ld r10,PACA_EXGEN+EX_R10(r13) |
663 | ld r11,PACA_EXGEN+EX_R11(r13) | 663 | ld r11,PACA_EXGEN+EX_R11(r13) |
@@ -713,8 +713,8 @@ bad_stack: | |||
713 | std r10,GPR1(r1) | 713 | std r10,GPR1(r1) |
714 | std r11,_NIP(r1) | 714 | std r11,_NIP(r1) |
715 | std r12,_MSR(r1) | 715 | std r12,_MSR(r1) |
716 | mfspr r11,DAR | 716 | mfspr r11,SPRN_DAR |
717 | mfspr r12,DSISR | 717 | mfspr r12,SPRN_DSISR |
718 | std r11,_DAR(r1) | 718 | std r11,_DAR(r1) |
719 | std r12,_DSISR(r1) | 719 | std r12,_DSISR(r1) |
720 | mflr r10 | 720 | mflr r10 |
@@ -766,8 +766,8 @@ fast_exception_return: | |||
766 | clrrdi r10,r10,2 /* clear RI (LE is 0 already) */ | 766 | clrrdi r10,r10,2 /* clear RI (LE is 0 already) */ |
767 | mtmsrd r10,1 | 767 | mtmsrd r10,1 |
768 | 768 | ||
769 | mtspr SRR1,r12 | 769 | mtspr SPRN_SRR1,r12 |
770 | mtspr SRR0,r11 | 770 | mtspr SPRN_SRR0,r11 |
771 | REST_4GPRS(10, r1) | 771 | REST_4GPRS(10, r1) |
772 | ld r1,GPR1(r1) | 772 | ld r1,GPR1(r1) |
773 | rfid | 773 | rfid |
@@ -788,9 +788,9 @@ unrecov_fer: | |||
788 | .globl data_access_common | 788 | .globl data_access_common |
789 | data_access_common: | 789 | data_access_common: |
790 | RUNLATCH_ON(r10) /* It wont fit in the 0x300 handler */ | 790 | RUNLATCH_ON(r10) /* It wont fit in the 0x300 handler */ |
791 | mfspr r10,DAR | 791 | mfspr r10,SPRN_DAR |
792 | std r10,PACA_EXGEN+EX_DAR(r13) | 792 | std r10,PACA_EXGEN+EX_DAR(r13) |
793 | mfspr r10,DSISR | 793 | mfspr r10,SPRN_DSISR |
794 | stw r10,PACA_EXGEN+EX_DSISR(r13) | 794 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
795 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | 795 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) |
796 | ld r3,PACA_EXGEN+EX_DAR(r13) | 796 | ld r3,PACA_EXGEN+EX_DAR(r13) |
@@ -821,9 +821,9 @@ hardware_interrupt_entry: | |||
821 | .align 7 | 821 | .align 7 |
822 | .globl alignment_common | 822 | .globl alignment_common |
823 | alignment_common: | 823 | alignment_common: |
824 | mfspr r10,DAR | 824 | mfspr r10,SPRN_DAR |
825 | std r10,PACA_EXGEN+EX_DAR(r13) | 825 | std r10,PACA_EXGEN+EX_DAR(r13) |
826 | mfspr r10,DSISR | 826 | mfspr r10,SPRN_DSISR |
827 | stw r10,PACA_EXGEN+EX_DSISR(r13) | 827 | stw r10,PACA_EXGEN+EX_DSISR(r13) |
828 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | 828 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) |
829 | ld r3,PACA_EXGEN+EX_DAR(r13) | 829 | ld r3,PACA_EXGEN+EX_DAR(r13) |
@@ -1064,7 +1064,7 @@ _GLOBAL(do_stab_bolted) | |||
1064 | 1064 | ||
1065 | /* Hash to the primary group */ | 1065 | /* Hash to the primary group */ |
1066 | ld r10,PACASTABVIRT(r13) | 1066 | ld r10,PACASTABVIRT(r13) |
1067 | mfspr r11,DAR | 1067 | mfspr r11,SPRN_DAR |
1068 | srdi r11,r11,28 | 1068 | srdi r11,r11,28 |
1069 | rldimi r10,r11,7,52 /* r10 = first ste of the group */ | 1069 | rldimi r10,r11,7,52 /* r10 = first ste of the group */ |
1070 | 1070 | ||
@@ -1106,7 +1106,7 @@ _GLOBAL(do_stab_bolted) | |||
1106 | 2: std r9,8(r10) /* Store the vsid part of the ste */ | 1106 | 2: std r9,8(r10) /* Store the vsid part of the ste */ |
1107 | eieio | 1107 | eieio |
1108 | 1108 | ||
1109 | mfspr r11,DAR /* Get the new esid */ | 1109 | mfspr r11,SPRN_DAR /* Get the new esid */ |
1110 | clrrdi r11,r11,28 /* Permits a full 32b of ESID */ | 1110 | clrrdi r11,r11,28 /* Permits a full 32b of ESID */ |
1111 | ori r11,r11,0x90 /* Turn on valid and kp */ | 1111 | ori r11,r11,0x90 /* Turn on valid and kp */ |
1112 | std r11,0(r10) /* Put new entry back into the stab */ | 1112 | std r11,0(r10) /* Put new entry back into the stab */ |
@@ -1126,8 +1126,8 @@ _GLOBAL(do_stab_bolted) | |||
1126 | clrrdi r10,r10,2 | 1126 | clrrdi r10,r10,2 |
1127 | mtmsrd r10,1 | 1127 | mtmsrd r10,1 |
1128 | 1128 | ||
1129 | mtspr SRR0,r11 | 1129 | mtspr SPRN_SRR0,r11 |
1130 | mtspr SRR1,r12 | 1130 | mtspr SPRN_SRR1,r12 |
1131 | ld r9,PACA_EXSLB+EX_R9(r13) | 1131 | ld r9,PACA_EXSLB+EX_R9(r13) |
1132 | ld r10,PACA_EXSLB+EX_R10(r13) | 1132 | ld r10,PACA_EXSLB+EX_R10(r13) |
1133 | ld r11,PACA_EXSLB+EX_R11(r13) | 1133 | ld r11,PACA_EXSLB+EX_R11(r13) |
@@ -1173,8 +1173,8 @@ _GLOBAL(do_slb_miss) | |||
1173 | .machine pop | 1173 | .machine pop |
1174 | 1174 | ||
1175 | #ifdef CONFIG_PPC_ISERIES | 1175 | #ifdef CONFIG_PPC_ISERIES |
1176 | mtspr SRR0,r11 | 1176 | mtspr SPRN_SRR0,r11 |
1177 | mtspr SRR1,r12 | 1177 | mtspr SPRN_SRR1,r12 |
1178 | #endif /* CONFIG_PPC_ISERIES */ | 1178 | #endif /* CONFIG_PPC_ISERIES */ |
1179 | ld r9,PACA_EXSLB+EX_R9(r13) | 1179 | ld r9,PACA_EXSLB+EX_R9(r13) |
1180 | ld r10,PACA_EXSLB+EX_R10(r13) | 1180 | ld r10,PACA_EXSLB+EX_R10(r13) |
@@ -1260,7 +1260,7 @@ _GLOBAL(pSeries_secondary_smp_init) | |||
1260 | mr r3,r24 /* not found, copy phys to r3 */ | 1260 | mr r3,r24 /* not found, copy phys to r3 */ |
1261 | b .kexec_wait /* next kernel might do better */ | 1261 | b .kexec_wait /* next kernel might do better */ |
1262 | 1262 | ||
1263 | 2: mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */ | 1263 | 2: mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ |
1264 | /* From now on, r24 is expected to be logical cpuid */ | 1264 | /* From now on, r24 is expected to be logical cpuid */ |
1265 | mr r24,r5 | 1265 | mr r24,r5 |
1266 | 3: HMT_LOW | 1266 | 3: HMT_LOW |
@@ -1531,7 +1531,7 @@ _GLOBAL(pmac_secondary_start) | |||
1531 | LOADADDR(r4, paca) /* Get base vaddr of paca array */ | 1531 | LOADADDR(r4, paca) /* Get base vaddr of paca array */ |
1532 | mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ | 1532 | mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */ |
1533 | add r13,r13,r4 /* for this processor. */ | 1533 | add r13,r13,r4 /* for this processor. */ |
1534 | mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */ | 1534 | mtspr SPRN_SPRG3,r13 /* Save vaddr of paca in SPRG3 */ |
1535 | 1535 | ||
1536 | /* Create a temp kernel stack for use before relocation is on. */ | 1536 | /* Create a temp kernel stack for use before relocation is on. */ |
1537 | ld r1,PACAEMERGSP(r13) | 1537 | ld r1,PACAEMERGSP(r13) |
@@ -1566,7 +1566,7 @@ _GLOBAL(__secondary_start) | |||
1566 | /* Initialize the page table pointer register. */ | 1566 | /* Initialize the page table pointer register. */ |
1567 | LOADADDR(r6,_SDR1) | 1567 | LOADADDR(r6,_SDR1) |
1568 | ld r6,0(r6) /* get the value of _SDR1 */ | 1568 | ld r6,0(r6) /* get the value of _SDR1 */ |
1569 | mtspr SDR1,r6 /* set the htab location */ | 1569 | mtspr SPRN_SDR1,r6 /* set the htab location */ |
1570 | #endif | 1570 | #endif |
1571 | /* Initialize the first segment table (or SLB) entry */ | 1571 | /* Initialize the first segment table (or SLB) entry */ |
1572 | ld r3,PACASTABVIRT(r13) /* get addr of segment table */ | 1572 | ld r3,PACASTABVIRT(r13) /* get addr of segment table */ |
@@ -1595,7 +1595,7 @@ _GLOBAL(__secondary_start) | |||
1595 | lwz r3,PLATFORM(r3) /* r3 = platform flags */ | 1595 | lwz r3,PLATFORM(r3) /* r3 = platform flags */ |
1596 | andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */ | 1596 | andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */ |
1597 | beq 98f /* branch if result is 0 */ | 1597 | beq 98f /* branch if result is 0 */ |
1598 | mfspr r3,PVR | 1598 | mfspr r3,SPRN_PVR |
1599 | srwi r3,r3,16 | 1599 | srwi r3,r3,16 |
1600 | cmpwi r3,0x37 /* SStar */ | 1600 | cmpwi r3,0x37 /* SStar */ |
1601 | beq 97f | 1601 | beq 97f |
@@ -1619,8 +1619,8 @@ _GLOBAL(__secondary_start) | |||
1619 | #ifdef DO_SOFT_DISABLE | 1619 | #ifdef DO_SOFT_DISABLE |
1620 | ori r4,r4,MSR_EE | 1620 | ori r4,r4,MSR_EE |
1621 | #endif | 1621 | #endif |
1622 | mtspr SRR0,r3 | 1622 | mtspr SPRN_SRR0,r3 |
1623 | mtspr SRR1,r4 | 1623 | mtspr SPRN_SRR1,r4 |
1624 | rfid | 1624 | rfid |
1625 | b . /* prevent speculative execution */ | 1625 | b . /* prevent speculative execution */ |
1626 | 1626 | ||
@@ -1682,7 +1682,7 @@ _STATIC(start_here_multiplatform) | |||
1682 | 1682 | ||
1683 | #ifdef CONFIG_HMT | 1683 | #ifdef CONFIG_HMT |
1684 | /* Start up the second thread on cpu 0 */ | 1684 | /* Start up the second thread on cpu 0 */ |
1685 | mfspr r3,PVR | 1685 | mfspr r3,SPRN_PVR |
1686 | srwi r3,r3,16 | 1686 | srwi r3,r3,16 |
1687 | cmpwi r3,0x34 /* Pulsar */ | 1687 | cmpwi r3,0x34 /* Pulsar */ |
1688 | beq 90f | 1688 | beq 90f |
@@ -1742,7 +1742,7 @@ _STATIC(start_here_multiplatform) | |||
1742 | mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */ | 1742 | mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */ |
1743 | add r13,r13,r24 /* for this processor. */ | 1743 | add r13,r13,r24 /* for this processor. */ |
1744 | sub r13,r13,r26 /* convert to physical addr */ | 1744 | sub r13,r13,r26 /* convert to physical addr */ |
1745 | mtspr SPRG3,r13 /* PPPBBB: Temp... -Peter */ | 1745 | mtspr SPRN_SPRG3,r13 /* PPPBBB: Temp... -Peter */ |
1746 | 1746 | ||
1747 | /* Do very early kernel initializations, including initial hash table, | 1747 | /* Do very early kernel initializations, including initial hash table, |
1748 | * stab and slb setup before we turn on relocation. */ | 1748 | * stab and slb setup before we turn on relocation. */ |
@@ -1759,7 +1759,7 @@ _STATIC(start_here_multiplatform) | |||
1759 | lwz r3,PLATFORM(r3) /* r3 = platform flags */ | 1759 | lwz r3,PLATFORM(r3) /* r3 = platform flags */ |
1760 | andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */ | 1760 | andi. r3,r3,PLATFORM_LPAR /* Test if bit 0 is set (LPAR bit) */ |
1761 | beq 98f /* branch if result is 0 */ | 1761 | beq 98f /* branch if result is 0 */ |
1762 | mfspr r3,PVR | 1762 | mfspr r3,SPRN_PVR |
1763 | srwi r3,r3,16 | 1763 | srwi r3,r3,16 |
1764 | cmpwi r3,0x37 /* SStar */ | 1764 | cmpwi r3,0x37 /* SStar */ |
1765 | beq 97f | 1765 | beq 97f |
@@ -1783,12 +1783,12 @@ _STATIC(start_here_multiplatform) | |||
1783 | LOADADDR(r6,_SDR1) /* Only if NOT LPAR */ | 1783 | LOADADDR(r6,_SDR1) /* Only if NOT LPAR */ |
1784 | sub r6,r6,r26 | 1784 | sub r6,r6,r26 |
1785 | ld r6,0(r6) /* get the value of _SDR1 */ | 1785 | ld r6,0(r6) /* get the value of _SDR1 */ |
1786 | mtspr SDR1,r6 /* set the htab location */ | 1786 | mtspr SPRN_SDR1,r6 /* set the htab location */ |
1787 | 98: | 1787 | 98: |
1788 | LOADADDR(r3,.start_here_common) | 1788 | LOADADDR(r3,.start_here_common) |
1789 | SET_REG_TO_CONST(r4, MSR_KERNEL) | 1789 | SET_REG_TO_CONST(r4, MSR_KERNEL) |
1790 | mtspr SRR0,r3 | 1790 | mtspr SPRN_SRR0,r3 |
1791 | mtspr SRR1,r4 | 1791 | mtspr SPRN_SRR1,r4 |
1792 | rfid | 1792 | rfid |
1793 | b . /* prevent speculative execution */ | 1793 | b . /* prevent speculative execution */ |
1794 | #endif /* CONFIG_PPC_MULTIPLATFORM */ | 1794 | #endif /* CONFIG_PPC_MULTIPLATFORM */ |
@@ -1819,7 +1819,7 @@ _STATIC(start_here_common) | |||
1819 | LOADADDR(r24, paca) /* Get base vaddr of paca array */ | 1819 | LOADADDR(r24, paca) /* Get base vaddr of paca array */ |
1820 | mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */ | 1820 | mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */ |
1821 | add r13,r13,r24 /* for this processor. */ | 1821 | add r13,r13,r24 /* for this processor. */ |
1822 | mtspr SPRG3,r13 | 1822 | mtspr SPRN_SPRG3,r13 |
1823 | 1823 | ||
1824 | /* ptr to current */ | 1824 | /* ptr to current */ |
1825 | LOADADDR(r4,init_task) | 1825 | LOADADDR(r4,init_task) |
@@ -1846,7 +1846,7 @@ _STATIC(start_here_common) | |||
1846 | _GLOBAL(hmt_init) | 1846 | _GLOBAL(hmt_init) |
1847 | #ifdef CONFIG_HMT | 1847 | #ifdef CONFIG_HMT |
1848 | LOADADDR(r5, hmt_thread_data) | 1848 | LOADADDR(r5, hmt_thread_data) |
1849 | mfspr r7,PVR | 1849 | mfspr r7,SPRN_PVR |
1850 | srwi r7,r7,16 | 1850 | srwi r7,r7,16 |
1851 | cmpwi r7,0x34 /* Pulsar */ | 1851 | cmpwi r7,0x34 /* Pulsar */ |
1852 | beq 90f | 1852 | beq 90f |
@@ -1855,10 +1855,10 @@ _GLOBAL(hmt_init) | |||
1855 | cmpwi r7,0x37 /* SStar */ | 1855 | cmpwi r7,0x37 /* SStar */ |
1856 | beq 91f | 1856 | beq 91f |
1857 | b 101f | 1857 | b 101f |
1858 | 90: mfspr r6,PIR | 1858 | 90: mfspr r6,SPRN_PIR |
1859 | andi. r6,r6,0x1f | 1859 | andi. r6,r6,0x1f |
1860 | b 92f | 1860 | b 92f |
1861 | 91: mfspr r6,PIR | 1861 | 91: mfspr r6,SPRN_PIR |
1862 | andi. r6,r6,0x3ff | 1862 | andi. r6,r6,0x3ff |
1863 | 92: sldi r4,r24,3 | 1863 | 92: sldi r4,r24,3 |
1864 | stwx r6,r5,r4 | 1864 | stwx r6,r5,r4 |
@@ -1869,8 +1869,8 @@ __hmt_secondary_hold: | |||
1869 | LOADADDR(r5, hmt_thread_data) | 1869 | LOADADDR(r5, hmt_thread_data) |
1870 | clrldi r5,r5,4 | 1870 | clrldi r5,r5,4 |
1871 | li r7,0 | 1871 | li r7,0 |
1872 | mfspr r6,PIR | 1872 | mfspr r6,SPRN_PIR |
1873 | mfspr r8,PVR | 1873 | mfspr r8,SPRN_PVR |
1874 | srwi r8,r8,16 | 1874 | srwi r8,r8,16 |
1875 | cmpwi r8,0x34 | 1875 | cmpwi r8,0x34 |
1876 | bne 93f | 1876 | bne 93f |
@@ -1896,19 +1896,19 @@ __hmt_secondary_hold: | |||
1896 | _GLOBAL(hmt_start_secondary) | 1896 | _GLOBAL(hmt_start_secondary) |
1897 | LOADADDR(r4,__hmt_secondary_hold) | 1897 | LOADADDR(r4,__hmt_secondary_hold) |
1898 | clrldi r4,r4,4 | 1898 | clrldi r4,r4,4 |
1899 | mtspr NIADORM, r4 | 1899 | mtspr SPRN_NIADORM, r4 |
1900 | mfspr r4, MSRDORM | 1900 | mfspr r4, SPRN_MSRDORM |
1901 | li r5, -65 | 1901 | li r5, -65 |
1902 | and r4, r4, r5 | 1902 | and r4, r4, r5 |
1903 | mtspr MSRDORM, r4 | 1903 | mtspr SPRN_MSRDORM, r4 |
1904 | lis r4,0xffef | 1904 | lis r4,0xffef |
1905 | ori r4,r4,0x7403 | 1905 | ori r4,r4,0x7403 |
1906 | mtspr TSC, r4 | 1906 | mtspr SPRN_TSC, r4 |
1907 | li r4,0x1f4 | 1907 | li r4,0x1f4 |
1908 | mtspr TST, r4 | 1908 | mtspr SPRN_TST, r4 |
1909 | mfspr r4, HID0 | 1909 | mfspr r4, SPRN_HID0 |
1910 | ori r4, r4, 0x1 | 1910 | ori r4, r4, 0x1 |
1911 | mtspr HID0, r4 | 1911 | mtspr SPRN_HID0, r4 |
1912 | mfspr r4, SPRN_CTRLF | 1912 | mfspr r4, SPRN_CTRLF |
1913 | oris r4, r4, 0x40 | 1913 | oris r4, r4, 0x40 |
1914 | mtspr SPRN_CTRLT, r4 | 1914 | mtspr SPRN_CTRLT, r4 |