powerpc/44x: Support 16K/64K base page sizes on 44x

This adds support for 16k and 64k page sizes on PowerPC 44x processors.

The PGDIR table is much smaller than a page when using 16k or 64k
pages (512 and 32 bytes respectively) so we allocate the PGDIR with
kzalloc() instead of __get_free_pages().

One PTE table covers rather a large memory area when using 16k or 64k
pages (32MB or 512MB respectively), so we can easily put FIXMAP and
PKMAP in the area covered by one PTE table.

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
Signed-off-by: Vladimir Panfilov <pvr@emcraft.com>
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 14 insertions, 9 deletions

diff --git a/arch/powerpc/kernel/head_44x.S b/arch/powerpc/kernel/head_44x.S
index bd4fe9e7278b..b56fecc93a16 100644
--- a/arch/powerpc/kernel/head_44x.S
+++ b/arch/powerpc/kernel/head_44x.S
@@ -402,12 +402,14 @@ interrupt_base:
         rlwimi  r13,r12,10,30,30
 
         /* Load the PTE */
-        rlwinm  r12, r10, 13, 19, 29    /* Compute pgdir/pmd offset */
+        /* Compute pgdir/pmd offset */
+        rlwinm  r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
         lwzx    r11, r12, r11           /* Get pgd/pmd entry */
         rlwinm. r12, r11, 0, 0, 20      /* Extract pt base address */
         beq     2f                      /* Bail if no table */
 
-        rlwimi  r12, r10, 23, 20, 28    /* Compute pte address */
+        /* Compute pte address */
+        rlwimi  r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
         lwz     r11, 0(r12)             /* Get high word of pte entry */
         lwz     r12, 4(r12)             /* Get low word of pte entry */
 
@@ -496,12 +498,14 @@ tlb_44x_patch_hwater_D:
         /* Make up the required permissions */
         li      r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC
 
-        rlwinm  r12, r10, 13, 19, 29    /* Compute pgdir/pmd offset */
+        /* Compute pgdir/pmd offset */
+        rlwinm  r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
         lwzx    r11, r12, r11           /* Get pgd/pmd entry */
         rlwinm. r12, r11, 0, 0, 20      /* Extract pt base address */
         beq     2f                      /* Bail if no table */
 
-        rlwimi  r12, r10, 23, 20, 28    /* Compute pte address */
+        /* Compute pte address */
+        rlwimi  r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
         lwz     r11, 0(r12)             /* Get high word of pte entry */
         lwz     r12, 4(r12)             /* Get low word of pte entry */
 
@@ -565,15 +569,16 @@ tlb_44x_patch_hwater_I:
  */
 finish_tlb_load:
         /* Combine RPN & ERPN an write WS 0 */
-        rlwimi  r11,r12,0,0,19
+        rlwimi  r11,r12,0,0,31-PAGE_SHIFT
         tlbwe   r11,r13,PPC44x_TLB_XLAT
 
         /*
          * Create WS1. This is the faulting address (EPN),
          * page size, and valid flag.
          */
-        li      r11,PPC44x_TLB_VALID | PPC44x_TLB_4K
-        rlwimi  r10,r11,0,20,31                 /* Insert valid and page size*/
+        li      r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE
+        /* Insert valid and page size */
+        rlwimi  r10,r11,0,PPC44x_PTE_ADD_MASK_BIT,31
         tlbwe   r10,r13,PPC44x_TLB_PAGEID       /* Write PAGEID */
 
         /* And WS 2 */
@@ -645,12 +650,12 @@ _GLOBAL(set_context)
  * goes at the beginning of the data segment, which is page-aligned.
  */
         .data
-        .align  12
+        .align  PAGE_SHIFT
         .globl  sdata
 sdata:
         .globl  empty_zero_page
 empty_zero_page:
-        .space  4096
+        .space  PAGE_SIZE
 
 /*
  * To support >32-bit physical addresses, we use an 8KB pgdir.