POWERPC: Allow 32-bit hashed pgtable code to support 36-bit physical

This rearranges a bit of code, and adds support for
36-bit physical addressing for configs that use a
hashed page table.  The 36b physical support is not
enabled by default on any config - it must be
explicitly enabled via the config system.

This patch *only* expands the page table code to accomodate
large physical addresses on 32-bit systems and enables the
PHYS_64BIT config option for 86xx.  It does *not*
allow you to boot a board with more than about 3.5GB of
RAM - for that, SWIOTLB support is also required (and
coming soon).

Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 8bb657519299..a6de6dbc5ed8 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -369,13 +369,13 @@ i##n:								\
 DataAccess:
         EXCEPTION_PROLOG
         mfspr   r10,SPRN_DSISR
+        stw     r10,_DSISR(r11)
         andis.  r0,r10,0xa470           /* weird error? */
         bne     1f                      /* if not, try to put a PTE */
         mfspr   r4,SPRN_DAR             /* into the hash table */
         rlwinm  r3,r10,32-15,21,21      /* DSISR_STORE -> _PAGE_RW */
         bl      hash_page
-1:      stw     r10,_DSISR(r11)
-        mr      r5,r10
+1:      lwz     r5,_DSISR(r11)          /* get DSISR value */
         mfspr   r4,SPRN_DAR
         EXC_XFER_EE_LITE(0x300, handle_page_fault)