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author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-09 13:03:44 -0500 |
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committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-09 13:03:44 -0500 |
commit | 6150c32589d1976ca8a5c987df951088c05a7542 (patch) | |
tree | 94073696576323ff966e365d8c47b8ecd8372f97 /arch/powerpc/kernel/head_32.S | |
parent | 44637a12f80b80157d9c1bc5b7d6ef09c9e05713 (diff) | |
parent | be42d5fa3772241b8ecebd443f1fb36247959c54 (diff) |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc-merge
Diffstat (limited to 'arch/powerpc/kernel/head_32.S')
-rw-r--r-- | arch/powerpc/kernel/head_32.S | 56 |
1 files changed, 50 insertions, 6 deletions
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index ccdf94731e30..03b25f9359f8 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S | |||
@@ -120,10 +120,25 @@ __start: | |||
120 | * because OF may have I/O devices mapped into that area | 120 | * because OF may have I/O devices mapped into that area |
121 | * (particularly on CHRP). | 121 | * (particularly on CHRP). |
122 | */ | 122 | */ |
123 | #ifdef CONFIG_PPC_MULTIPLATFORM | ||
123 | cmpwi 0,r5,0 | 124 | cmpwi 0,r5,0 |
124 | beq 1f | 125 | beq 1f |
125 | bl prom_init | 126 | bl prom_init |
126 | trap | 127 | trap |
128 | #endif | ||
129 | |||
130 | /* | ||
131 | * Check for BootX signature when supporting PowerMac and branch to | ||
132 | * appropriate trampoline if it's present | ||
133 | */ | ||
134 | #ifdef CONFIG_PPC_PMAC | ||
135 | 1: lis r31,0x426f | ||
136 | ori r31,r31,0x6f58 | ||
137 | cmpw 0,r3,r31 | ||
138 | bne 1f | ||
139 | bl bootx_init | ||
140 | trap | ||
141 | #endif /* CONFIG_PPC_PMAC */ | ||
127 | 142 | ||
128 | 1: mr r31,r3 /* save parameters */ | 143 | 1: mr r31,r3 /* save parameters */ |
129 | mr r30,r4 | 144 | mr r30,r4 |
@@ -153,6 +168,9 @@ __after_mmu_off: | |||
153 | bl flush_tlbs | 168 | bl flush_tlbs |
154 | 169 | ||
155 | bl initial_bats | 170 | bl initial_bats |
171 | #if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) | ||
172 | bl setup_disp_bat | ||
173 | #endif | ||
156 | 174 | ||
157 | /* | 175 | /* |
158 | * Call setup_cpu for CPU 0 and initialize 6xx Idle | 176 | * Call setup_cpu for CPU 0 and initialize 6xx Idle |
@@ -450,16 +468,11 @@ SystemCall: | |||
450 | * by executing an altivec instruction. | 468 | * by executing an altivec instruction. |
451 | */ | 469 | */ |
452 | . = 0xf00 | 470 | . = 0xf00 |
453 | b Trap_0f | 471 | b PerformanceMonitor |
454 | 472 | ||
455 | . = 0xf20 | 473 | . = 0xf20 |
456 | b AltiVecUnavailable | 474 | b AltiVecUnavailable |
457 | 475 | ||
458 | Trap_0f: | ||
459 | EXCEPTION_PROLOG | ||
460 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
461 | EXC_XFER_EE(0xf00, unknown_exception) | ||
462 | |||
463 | /* | 476 | /* |
464 | * Handle TLB miss for instruction on 603/603e. | 477 | * Handle TLB miss for instruction on 603/603e. |
465 | * Note: we get an alternate set of r0 - r3 to use automatically. | 478 | * Note: we get an alternate set of r0 - r3 to use automatically. |
@@ -703,6 +716,11 @@ AltiVecUnavailable: | |||
703 | #endif /* CONFIG_ALTIVEC */ | 716 | #endif /* CONFIG_ALTIVEC */ |
704 | EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception) | 717 | EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception) |
705 | 718 | ||
719 | PerformanceMonitor: | ||
720 | EXCEPTION_PROLOG | ||
721 | addi r3,r1,STACK_FRAME_OVERHEAD | ||
722 | EXC_XFER_STD(0xf00, performance_monitor_exception) | ||
723 | |||
706 | #ifdef CONFIG_ALTIVEC | 724 | #ifdef CONFIG_ALTIVEC |
707 | /* Note that the AltiVec support is closely modeled after the FP | 725 | /* Note that the AltiVec support is closely modeled after the FP |
708 | * support. Changes to one are likely to be applicable to the | 726 | * support. Changes to one are likely to be applicable to the |
@@ -1306,6 +1324,32 @@ initial_bats: | |||
1306 | blr | 1324 | blr |
1307 | 1325 | ||
1308 | 1326 | ||
1327 | #if !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) | ||
1328 | setup_disp_bat: | ||
1329 | /* | ||
1330 | * setup the display bat prepared for us in prom.c | ||
1331 | */ | ||
1332 | mflr r8 | ||
1333 | bl reloc_offset | ||
1334 | mtlr r8 | ||
1335 | addis r8,r3,disp_BAT@ha | ||
1336 | addi r8,r8,disp_BAT@l | ||
1337 | cmpwi cr0,r8,0 | ||
1338 | beqlr | ||
1339 | lwz r11,0(r8) | ||
1340 | lwz r8,4(r8) | ||
1341 | mfspr r9,SPRN_PVR | ||
1342 | rlwinm r9,r9,16,16,31 /* r9 = 1 for 601, 4 for 604 */ | ||
1343 | cmpwi 0,r9,1 | ||
1344 | beq 1f | ||
1345 | mtspr SPRN_DBAT3L,r8 | ||
1346 | mtspr SPRN_DBAT3U,r11 | ||
1347 | blr | ||
1348 | 1: mtspr SPRN_IBAT3L,r8 | ||
1349 | mtspr SPRN_IBAT3U,r11 | ||
1350 | blr | ||
1351 | #endif /* !defined(CONFIG_APUS) && defined(CONFIG_BOOTX_TEXT) */ | ||
1352 | |||
1309 | #ifdef CONFIG_8260 | 1353 | #ifdef CONFIG_8260 |
1310 | /* Jump into the system reset for the rom. | 1354 | /* Jump into the system reset for the rom. |
1311 | * We first disable the MMU, and then jump to the ROM reset address. | 1355 | * We first disable the MMU, and then jump to the ROM reset address. |