diff options
author | Anton Blanchard <anton@samba.org> | 2006-06-10 06:18:39 -0400 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2006-06-15 05:31:25 -0400 |
commit | 3a2c48cfc97f9046abbd810f1efb1aa824bcfaf1 (patch) | |
tree | afcd54f2ad36353abcf2282fdf15a05e77fcba4a /arch/powerpc/kernel/fpu.S | |
parent | 30d8caf7c625203b295a78f143820cdc3124830b (diff) |
[POWERPC] 64bit FPSCR support
Forthcoming machines will extend the FPSCR to 64 bits. We already
had a 64-bit save area for the FPSCR, but we need to use a new form
of the mtfsf instruction. Fortunately this new form is decoded as
an ordinary mtfsf by existing 64-bit processors.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/kernel/fpu.S')
-rw-r--r-- | arch/powerpc/kernel/fpu.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S index 340730fb8c91..01f71200c603 100644 --- a/arch/powerpc/kernel/fpu.S +++ b/arch/powerpc/kernel/fpu.S | |||
@@ -72,7 +72,7 @@ _GLOBAL(load_up_fpu) | |||
72 | std r12,_MSR(r1) | 72 | std r12,_MSR(r1) |
73 | #endif | 73 | #endif |
74 | lfd fr0,THREAD_FPSCR(r5) | 74 | lfd fr0,THREAD_FPSCR(r5) |
75 | mtfsf 0xff,fr0 | 75 | MTFSF_L(fr0) |
76 | REST_32FPRS(0, r5) | 76 | REST_32FPRS(0, r5) |
77 | #ifndef CONFIG_SMP | 77 | #ifndef CONFIG_SMP |
78 | subi r4,r5,THREAD | 78 | subi r4,r5,THREAD |
@@ -127,7 +127,7 @@ _GLOBAL(giveup_fpu) | |||
127 | 127 | ||
128 | _GLOBAL(cvt_fd) | 128 | _GLOBAL(cvt_fd) |
129 | lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */ | 129 | lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */ |
130 | mtfsf 0xff,0 | 130 | MTFSF_L(0) |
131 | lfs 0,0(r3) | 131 | lfs 0,0(r3) |
132 | stfd 0,0(r4) | 132 | stfd 0,0(r4) |
133 | mffs 0 | 133 | mffs 0 |
@@ -136,7 +136,7 @@ _GLOBAL(cvt_fd) | |||
136 | 136 | ||
137 | _GLOBAL(cvt_df) | 137 | _GLOBAL(cvt_df) |
138 | lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */ | 138 | lfd 0,THREAD_FPSCR(r5) /* load up fpscr value */ |
139 | mtfsf 0xff,0 | 139 | MTFSF_L(0) |
140 | lfd 0,0(r3) | 140 | lfd 0,0(r3) |
141 | stfs 0,0(r4) | 141 | stfs 0,0(r4) |
142 | mffs 0 | 142 | mffs 0 |