powerpc: Add VSX context save/restore, ptrace and signal support

This patch extends the floating point save and restore code to use the
VSX load/stores when VSX is available.  This will make FP context
save/restore marginally slower on FP only code, when VSX is available,
as it has to load/store 128bits rather than just 64bits.

Mixing FP, VMX and VSX code will get constant architected state.

The signals interface is extended to enable access to VSR 0-31
doubleword 1 after discussions with tool chain maintainers.  Backward
compatibility is maintained.

The ptrace interface is also extended to allow access to VSR 0-31 full
registers.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 13 insertions, 3 deletions

diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index 15247fe171a8..a088c064ae40 100644
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -57,6 +57,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX);					\
 _GLOBAL(load_up_fpu)
         mfmsr   r5
         ori     r5,r5,MSR_FP
+#ifdef CONFIG_VSX
+BEGIN_FTR_SECTION
+        oris    r5,r5,MSR_VSX@h
+END_FTR_SECTION_IFSET(CPU_FTR_VSX)
+#endif
         SYNC
         MTMSRD(r5)                      /* enable use of fpu now */
         isync
@@ -73,7 +78,7 @@ _GLOBAL(load_up_fpu)
         beq     1f
         toreal(r4)
         addi    r4,r4,THREAD            /* want last_task_used_math->thread */
-        SAVE_32FPRS(0, r4)
+        SAVE_32FPVSRS(0, r5, r4)
         mffs    fr0
         stfd    fr0,THREAD_FPSCR(r4)
         PPC_LL  r5,PT_REGS(r4)
@@ -100,7 +105,7 @@ _GLOBAL(load_up_fpu)
 #endif
         lfd     fr0,THREAD_FPSCR(r5)
         MTFSF_L(fr0)
-        REST_32FPRS(0, r5)
+        REST_32FPVSRS(0, r4, r5)
 #ifndef CONFIG_SMP
         subi    r4,r5,THREAD
         fromreal(r4)
@@ -119,6 +124,11 @@ _GLOBAL(load_up_fpu)
 _GLOBAL(giveup_fpu)
         mfmsr   r5
         ori     r5,r5,MSR_FP
+#ifdef CONFIG_VSX
+BEGIN_FTR_SECTION
+        oris    r5,r5,MSR_VSX@h
+END_FTR_SECTION_IFSET(CPU_FTR_VSX)
+#endif
         SYNC_601
         ISYNC_601
         MTMSRD(r5)                      /* enable use of fpu now */
@@ -129,7 +139,7 @@ _GLOBAL(giveup_fpu)
         addi    r3,r3,THREAD            /* want THREAD of task */
         PPC_LL  r5,PT_REGS(r3)
         PPC_LCMPI       0,r5,0
-        SAVE_32FPRS(0, r3)
+        SAVE_32FPVSRS(0, r4 ,r3)
         mffs    fr0
         stfd    fr0,THREAD_FPSCR(r3)
         beq     1f