aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/kernel/exceptions-64s.S
diff options
context:
space:
mode:
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-07-16 15:36:57 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-08-19 20:12:28 -0400
commitc5a8c0c99f67ae8a784faafbaaea1529825796e2 (patch)
tree731b07d0ac0414dbeac5ce940fe59a04a8d63c3f /arch/powerpc/kernel/exceptions-64s.S
parentee43eb788b3a06425fffb912677e2e1c8b00dd3b (diff)
powerpc: Remove use of a second scratch SPRG in STAB code
The STAB code used on Power3 and RS/64 uses a second scratch SPRG to save a GPR in order to decide whether to go to do_stab_bolted_* or to handle a normal data access exception. This prevents our scheme of freeing SPRG3 which is user visible for user uses since we cannot use SPRG0 which, on RS/64, seems to be read-only for supervisor mode (like POWER4). This reworks the STAB exception entry to use the PACA as temporary storage instead. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel/exceptions-64s.S')
-rw-r--r--arch/powerpc/kernel/exceptions-64s.S38
1 files changed, 25 insertions, 13 deletions
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 4e9640cc0563..50f2ad36ed09 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -50,18 +50,28 @@ data_access_pSeries:
50 HMT_MEDIUM 50 HMT_MEDIUM
51 mtspr SPRN_SPRG_SCRATCH0,r13 51 mtspr SPRN_SPRG_SCRATCH0,r13
52BEGIN_FTR_SECTION 52BEGIN_FTR_SECTION
53 mtspr SPRN_SPRG_SCRATCH1,r12 53 mfspr r13,SPRN_SPRG_PACA
54 mfspr r13,SPRN_DAR 54 std r9,PACA_EXSLB+EX_R9(r13)
55 mfspr r12,SPRN_DSISR 55 std r10,PACA_EXSLB+EX_R10(r13)
56 srdi r13,r13,60 56 mfspr r10,SPRN_DAR
57 rlwimi r13,r12,16,0x20 57 mfspr r9,SPRN_DSISR
58 mfcr r12 58 srdi r10,r10,60
59 cmpwi r13,0x2c 59 rlwimi r10,r9,16,0x20
60 mfcr r9
61 cmpwi r10,0x2c
60 beq do_stab_bolted_pSeries 62 beq do_stab_bolted_pSeries
61 mtcrf 0x80,r12 63 ld r10,PACA_EXSLB+EX_R10(r13)
62 mfspr r12,SPRN_SPRG_SCRATCH1 64 std r11,PACA_EXGEN+EX_R11(r13)
63END_FTR_SECTION_IFCLR(CPU_FTR_SLB) 65 ld r11,PACA_EXSLB+EX_R9(r13)
66 std r12,PACA_EXGEN+EX_R12(r13)
67 mfspr r12,SPRN_SPRG_SCRATCH0
68 std r10,PACA_EXGEN+EX_R10(r13)
69 std r11,PACA_EXGEN+EX_R9(r13)
70 std r12,PACA_EXGEN+EX_R13(r13)
71 EXCEPTION_PROLOG_PSERIES_1(data_access_common)
72FTR_SECTION_ELSE
64 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common) 73 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common)
74ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
65 75
66 . = 0x380 76 . = 0x380
67 .globl data_access_slb_pSeries 77 .globl data_access_slb_pSeries
@@ -224,9 +234,11 @@ masked_interrupt:
224 234
225 .align 7 235 .align 7
226do_stab_bolted_pSeries: 236do_stab_bolted_pSeries:
227 mtcrf 0x80,r12 237 std r11,PACA_EXSLB+EX_R11(r13)
228 mfspr r12,SPRN_SPRG_SCRATCH1 238 std r12,PACA_EXSLB+EX_R12(r13)
229 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted) 239 mfspr r10,SPRN_SPRG_SCRATCH0
240 std r10,PACA_EXSLB+EX_R13(r13)
241 EXCEPTION_PROLOG_PSERIES_1(.do_stab_bolted)
230 242
231#ifdef CONFIG_PPC_PSERIES 243#ifdef CONFIG_PPC_PSERIES
232/* 244/*