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authorPaul Mackerras <paulus@samba.org>2011-06-28 20:26:11 -0400
committerAvi Kivity <avi@redhat.com>2011-07-12 06:16:58 -0400
commit969391c58a4efb8411d6881179945f425ad9cbb5 (patch)
tree77ec5f178feee26c453033b7456ad789d3393482 /arch/powerpc/kernel/exceptions-64s.S
parentaa04b4cc5be64b4fb9ef4e0fdf2418e2f4737fb2 (diff)
powerpc, KVM: Split HVMODE_206 cpu feature bit into separate HV and architecture bits
This replaces the single CPU_FTR_HVMODE_206 bit with two bits, one to indicate that we have a usable hypervisor mode, and another to indicate that the processor conforms to PowerISA version 2.06. We also add another bit to indicate that the processor conforms to ISA version 2.01 and set that for PPC970 and derivatives. Some PPC970 chips (specifically those in Apple machines) have a hypervisor mode in that MSR[HV] is always 1, but the hypervisor mode is not useful in the sense that there is no way to run any code in supervisor mode (HV=0 PR=0). On these processors, the LPES0 and LPES1 bits in HID4 are always 0, and we use that as a way of detecting that hypervisor mode is not useful. Where we have a feature section in assembly code around code that only applies on POWER7 in hypervisor mode, we use a construct like END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) The definition of END_FTR_SECTION_IFSET is such that the code will be enabled (not overwritten with nops) only if all bits in the provided mask are set. Note that the CPU feature check in __tlbie() only needs to check the ARCH_206 bit, not the HVMODE bit, because __tlbie() can only get called if we are running bare-metal, i.e. in hypervisor mode. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'arch/powerpc/kernel/exceptions-64s.S')
-rw-r--r--arch/powerpc/kernel/exceptions-64s.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 5bc06fdfa6c0..a5345380bef3 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -75,7 +75,7 @@ BEGIN_FTR_SECTION
75 b .power7_wakeup_noloss 75 b .power7_wakeup_noloss
762: b .power7_wakeup_loss 762: b .power7_wakeup_loss
779: 779:
78END_FTR_SECTION_IFSET(CPU_FTR_HVMODE_206) 78END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
79#endif /* CONFIG_PPC_P7_NAP */ 79#endif /* CONFIG_PPC_P7_NAP */
80 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, 80 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD,
81 NOTEST, 0x100) 81 NOTEST, 0x100)
@@ -173,7 +173,7 @@ hardware_interrupt_hv:
173 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt, 173 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt,
174 EXC_STD, SOFTEN_TEST_PR) 174 EXC_STD, SOFTEN_TEST_PR)
175 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500) 175 KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500)
176 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE_206) 176 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
177 177
178 STD_EXCEPTION_PSERIES(0x600, 0x600, alignment) 178 STD_EXCEPTION_PSERIES(0x600, 0x600, alignment)
179 KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x600) 179 KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x600)