aboutsummaryrefslogtreecommitdiffstats
path: root/arch/powerpc/kernel/entry_32.S
diff options
context:
space:
mode:
authorKumar Gala <galak@kernel.crashing.org>2007-09-13 02:44:20 -0400
committerKumar Gala <galak@kernel.crashing.org>2007-09-14 09:53:30 -0400
commit5e14d21e3f28a4181dacff0336040e30942f4921 (patch)
treeebaa8217d5af80e15116960641a0bf87a8b5d717 /arch/powerpc/kernel/entry_32.S
parentd8f1324a5063c833862328ceafabc53ac3cc4f71 (diff)
[POWERPC] Add cpu feature for SPE handling
Make it so that SPE support can be determined at runtime. This is similiar to how we handle AltiVec. This allows us to have SPE support built in and work on processors with and without SPE. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel/entry_32.S')
-rw-r--r--arch/powerpc/kernel/entry_32.S4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 4074c0b31453..21d889e63e87 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -504,9 +504,11 @@ BEGIN_FTR_SECTION
504END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 504END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
505#endif /* CONFIG_ALTIVEC */ 505#endif /* CONFIG_ALTIVEC */
506#ifdef CONFIG_SPE 506#ifdef CONFIG_SPE
507BEGIN_FTR_SECTION
507 oris r0,r0,MSR_SPE@h /* Disable SPE */ 508 oris r0,r0,MSR_SPE@h /* Disable SPE */
508 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */ 509 mfspr r12,SPRN_SPEFSCR /* save spefscr register value */
509 stw r12,THREAD+THREAD_SPEFSCR(r2) 510 stw r12,THREAD+THREAD_SPEFSCR(r2)
511END_FTR_SECTION_IFSET(CPU_FTR_SPE)
510#endif /* CONFIG_SPE */ 512#endif /* CONFIG_SPE */
511 and. r0,r0,r11 /* FP or altivec or SPE enabled? */ 513 and. r0,r0,r11 /* FP or altivec or SPE enabled? */
512 beq+ 1f 514 beq+ 1f
@@ -542,8 +544,10 @@ BEGIN_FTR_SECTION
542END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 544END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
543#endif /* CONFIG_ALTIVEC */ 545#endif /* CONFIG_ALTIVEC */
544#ifdef CONFIG_SPE 546#ifdef CONFIG_SPE
547BEGIN_FTR_SECTION
545 lwz r0,THREAD+THREAD_SPEFSCR(r2) 548 lwz r0,THREAD+THREAD_SPEFSCR(r2)
546 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */ 549 mtspr SPRN_SPEFSCR,r0 /* restore SPEFSCR reg */
550END_FTR_SECTION_IFSET(CPU_FTR_SPE)
547#endif /* CONFIG_SPE */ 551#endif /* CONFIG_SPE */
548 552
549 lwz r0,_CCR(r1) 553 lwz r0,_CCR(r1)