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authorKumar Gala <galak@kernel.crashing.org>2009-02-10 15:10:44 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2009-02-22 18:48:56 -0500
commit16c57b3620d77e0bc981da5ef32beae730512684 (patch)
tree115045916a264f56f55751ce2948d59e03b16c0c /arch/powerpc/kernel/entry_32.S
parentbb9b903527eb16c8fdad59a562c29e89f5dcf233 (diff)
powerpc: Unify opcode definitions and support
Create a new header that becomes a single location for defining PowerPC opcodes used by code that is either generationg instructions at runtime (fixups, debug, etc.), emulating instructions, or just compiling instructions old assemblers don't know about. We currently don't handle the floating point emulation or alignment decode as both are better handled by the specific decode support they already have. Added support for the new dcbzl, dcbal, msgsnd, tlbilx, & wait instructions since older assemblers don't know about them. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel/entry_32.S')
-rw-r--r--arch/powerpc/kernel/entry_32.S8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/powerpc/kernel/entry_32.S b/arch/powerpc/kernel/entry_32.S
index 0506f54b4237..4dd38f129153 100644
--- a/arch/powerpc/kernel/entry_32.S
+++ b/arch/powerpc/kernel/entry_32.S
@@ -956,7 +956,7 @@ ret_from_crit_exc:
956 lwz r10,crit_srr1@l(r10); 956 lwz r10,crit_srr1@l(r10);
957 mtspr SPRN_SRR0,r9; 957 mtspr SPRN_SRR0,r9;
958 mtspr SPRN_SRR1,r10; 958 mtspr SPRN_SRR1,r10;
959 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, RFCI) 959 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
960#endif /* CONFIG_40x */ 960#endif /* CONFIG_40x */
961 961
962#ifdef CONFIG_BOOKE 962#ifdef CONFIG_BOOKE
@@ -967,7 +967,7 @@ ret_from_crit_exc:
967 stw r10,KSP_LIMIT(r9) 967 stw r10,KSP_LIMIT(r9)
968 RESTORE_xSRR(SRR0,SRR1); 968 RESTORE_xSRR(SRR0,SRR1);
969 RESTORE_MMU_REGS; 969 RESTORE_MMU_REGS;
970 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, RFCI) 970 RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, PPC_RFCI)
971 971
972 .globl ret_from_debug_exc 972 .globl ret_from_debug_exc
973ret_from_debug_exc: 973ret_from_debug_exc:
@@ -981,7 +981,7 @@ ret_from_debug_exc:
981 RESTORE_xSRR(SRR0,SRR1); 981 RESTORE_xSRR(SRR0,SRR1);
982 RESTORE_xSRR(CSRR0,CSRR1); 982 RESTORE_xSRR(CSRR0,CSRR1);
983 RESTORE_MMU_REGS; 983 RESTORE_MMU_REGS;
984 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, RFDI) 984 RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, PPC_RFDI)
985 985
986 .globl ret_from_mcheck_exc 986 .globl ret_from_mcheck_exc
987ret_from_mcheck_exc: 987ret_from_mcheck_exc:
@@ -992,7 +992,7 @@ ret_from_mcheck_exc:
992 RESTORE_xSRR(CSRR0,CSRR1); 992 RESTORE_xSRR(CSRR0,CSRR1);
993 RESTORE_xSRR(DSRR0,DSRR1); 993 RESTORE_xSRR(DSRR0,DSRR1);
994 RESTORE_MMU_REGS; 994 RESTORE_MMU_REGS;
995 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, RFMCI) 995 RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, PPC_RFMCI)
996#endif /* CONFIG_BOOKE */ 996#endif /* CONFIG_BOOKE */
997 997
998/* 998/*