powerpc/40x: Add APM8018X SOC support

The AppliedMicro APM8018X embedded processor targets embedded applications that
require low power and a small footprint. It features a PowerPC 405 processor
core built in a 65nm low-power CMOS process with a five-stage pipeline executing
up to one instruction per cycle. The family has 128-kbytes of on-chip memory,
a 128-bit local bus and on-chip DDR2 SDRAM controller with 16-bit interface.

Signed-off-by: Tanmay Inamdar <tinamdar@apm.com>
Signed-off-by: Josh Boyer <jwboyer@gmail.com>

1 files changed, 13 insertions, 0 deletions

diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index edae5bb06f1f..ce59693835c7 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1505,6 +1505,19 @@ static struct cpu_spec __initdata cpu_specs[] = {
                 .machine_check          = machine_check_4xx,
                 .platform               = "ppc405",
         },
+        {       /* APM8018X */
+                .pvr_mask               = 0xffff0000,
+                .pvr_value              = 0x7ff11432,
+                .cpu_name               = "APM8018X",
+                .cpu_features           = CPU_FTRS_40X,
+                .cpu_user_features      = PPC_FEATURE_32 |
+                        PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
+                .mmu_features           = MMU_FTR_TYPE_40x,
+                .icache_bsize           = 32,
+                .dcache_bsize           = 32,
+                .machine_check          = machine_check_4xx,
+                .platform               = "ppc405",
+        },
         {       /* default match */
                 .pvr_mask               = 0x00000000,
                 .pvr_value              = 0x00000000,