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authorStephen Rothwell <sfr@canb.auug.org.au>2005-10-12 01:55:09 -0400
committerStephen Rothwell <sfr@canb.auug.org.au>2005-10-12 19:49:45 -0400
commit4920960f577edcb0a5ef03823a53911cca5875e1 (patch)
treec37bb1a8b02f54e3a5012bac7f726208e6fc488e /arch/powerpc/kernel/cputable.c
parent7e130edf712ac054aecf643f9d3d0142a9679e6a (diff)
powerpc: consolidate cputable.c
Also simplify arch/ppc64/kernel/Makefile Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Diffstat (limited to 'arch/powerpc/kernel/cputable.c')
-rw-r--r--arch/powerpc/kernel/cputable.c997
1 files changed, 997 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
new file mode 100644
index 000000000000..214f3b088edf
--- /dev/null
+++ b/arch/powerpc/kernel/cputable.c
@@ -0,0 +1,997 @@
1/*
2 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
3 *
4 * Modifications for ppc64:
5 * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <linux/config.h>
14#include <linux/string.h>
15#include <linux/sched.h>
16#include <linux/threads.h>
17#include <linux/init.h>
18#include <linux/module.h>
19
20#include <asm/oprofile_impl.h>
21#include <asm/cputable.h>
22
23struct cpu_spec* cur_cpu_spec = NULL;
24#ifdef CONFIG_PPC64
25EXPORT_SYMBOL(cur_cpu_spec);
26#endif
27
28/* NOTE:
29 * Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
30 * the responsibility of the appropriate CPU save/restore functions to
31 * eventually copy these settings over. Those save/restore aren't yet
32 * part of the cputable though. That has to be fixed for both ppc32
33 * and ppc64
34 */
35#ifdef CONFIG_PPC64
36extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
37extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
38extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
39#else
40extern void __setup_cpu_603(unsigned long offset, struct cpu_spec* spec);
41extern void __setup_cpu_604(unsigned long offset, struct cpu_spec* spec);
42extern void __setup_cpu_750(unsigned long offset, struct cpu_spec* spec);
43extern void __setup_cpu_750cx(unsigned long offset, struct cpu_spec* spec);
44extern void __setup_cpu_750fx(unsigned long offset, struct cpu_spec* spec);
45extern void __setup_cpu_7400(unsigned long offset, struct cpu_spec* spec);
46extern void __setup_cpu_7410(unsigned long offset, struct cpu_spec* spec);
47extern void __setup_cpu_745x(unsigned long offset, struct cpu_spec* spec);
48#endif /* CONFIG_PPC32 */
49extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
50
51/* This table only contains "desktop" CPUs, it need to be filled with embedded
52 * ones as well...
53 */
54#define COMMON_USER (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
55 PPC_FEATURE_HAS_MMU)
56#define COMMON_USER_PPC64 (COMMON_USER | PPC_FEATURE_64)
57
58
59/* We only set the spe features if the kernel was compiled with
60 * spe support
61 */
62#ifdef CONFIG_SPE
63#define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE
64#else
65#define PPC_FEATURE_SPE_COMP 0
66#endif
67
68struct cpu_spec cpu_specs[] = {
69#ifdef CONFIG_PPC64
70 { /* Power3 */
71 .pvr_mask = 0xffff0000,
72 .pvr_value = 0x00400000,
73 .cpu_name = "POWER3 (630)",
74 .cpu_features = CPU_FTRS_POWER3,
75 .cpu_user_features = COMMON_USER_PPC64,
76 .icache_bsize = 128,
77 .dcache_bsize = 128,
78 .num_pmcs = 8,
79 .cpu_setup = __setup_cpu_power3,
80#ifdef CONFIG_OPROFILE
81 .oprofile_cpu_type = "ppc64/power3",
82 .oprofile_model = &op_model_rs64,
83#endif
84 },
85 { /* Power3+ */
86 .pvr_mask = 0xffff0000,
87 .pvr_value = 0x00410000,
88 .cpu_name = "POWER3 (630+)",
89 .cpu_features = CPU_FTRS_POWER3,
90 .cpu_user_features = COMMON_USER_PPC64,
91 .icache_bsize = 128,
92 .dcache_bsize = 128,
93 .num_pmcs = 8,
94 .cpu_setup = __setup_cpu_power3,
95#ifdef CONFIG_OPROFILE
96 .oprofile_cpu_type = "ppc64/power3",
97 .oprofile_model = &op_model_rs64,
98#endif
99 },
100 { /* Northstar */
101 .pvr_mask = 0xffff0000,
102 .pvr_value = 0x00330000,
103 .cpu_name = "RS64-II (northstar)",
104 .cpu_features = CPU_FTRS_RS64,
105 .cpu_user_features = COMMON_USER_PPC64,
106 .icache_bsize = 128,
107 .dcache_bsize = 128,
108 .num_pmcs = 8,
109 .cpu_setup = __setup_cpu_power3,
110#ifdef CONFIG_OPROFILE
111 .oprofile_cpu_type = "ppc64/rs64",
112 .oprofile_model = &op_model_rs64,
113#endif
114 },
115 { /* Pulsar */
116 .pvr_mask = 0xffff0000,
117 .pvr_value = 0x00340000,
118 .cpu_name = "RS64-III (pulsar)",
119 .cpu_features = CPU_FTRS_RS64,
120 .cpu_user_features = COMMON_USER_PPC64,
121 .icache_bsize = 128,
122 .dcache_bsize = 128,
123 .num_pmcs = 8,
124 .cpu_setup = __setup_cpu_power3,
125#ifdef CONFIG_OPROFILE
126 .oprofile_cpu_type = "ppc64/rs64",
127 .oprofile_model = &op_model_rs64,
128#endif
129 },
130 { /* I-star */
131 .pvr_mask = 0xffff0000,
132 .pvr_value = 0x00360000,
133 .cpu_name = "RS64-III (icestar)",
134 .cpu_features = CPU_FTRS_RS64,
135 .cpu_user_features = COMMON_USER_PPC64,
136 .icache_bsize = 128,
137 .dcache_bsize = 128,
138 .num_pmcs = 8,
139 .cpu_setup = __setup_cpu_power3,
140#ifdef CONFIG_OPROFILE
141 .oprofile_cpu_type = "ppc64/rs64",
142 .oprofile_model = &op_model_rs64,
143#endif
144 },
145 { /* S-star */
146 .pvr_mask = 0xffff0000,
147 .pvr_value = 0x00370000,
148 .cpu_name = "RS64-IV (sstar)",
149 .cpu_features = CPU_FTRS_RS64,
150 .cpu_user_features = COMMON_USER_PPC64,
151 .icache_bsize = 128,
152 .dcache_bsize = 128,
153 .num_pmcs = 8,
154 .cpu_setup = __setup_cpu_power3,
155#ifdef CONFIG_OPROFILE
156 .oprofile_cpu_type = "ppc64/rs64",
157 .oprofile_model = &op_model_rs64,
158#endif
159 },
160 { /* Power4 */
161 .pvr_mask = 0xffff0000,
162 .pvr_value = 0x00350000,
163 .cpu_name = "POWER4 (gp)",
164 .cpu_features = CPU_FTRS_POWER4,
165 .cpu_user_features = COMMON_USER_PPC64,
166 .icache_bsize = 128,
167 .dcache_bsize = 128,
168 .num_pmcs = 8,
169 .cpu_setup = __setup_cpu_power4,
170#ifdef CONFIG_OPROFILE
171 .oprofile_cpu_type = "ppc64/power4",
172 .oprofile_model = &op_model_rs64,
173#endif
174 },
175 { /* Power4+ */
176 .pvr_mask = 0xffff0000,
177 .pvr_value = 0x00380000,
178 .cpu_name = "POWER4+ (gq)",
179 .cpu_features = CPU_FTRS_POWER4,
180 .cpu_user_features = COMMON_USER_PPC64,
181 .icache_bsize = 128,
182 .dcache_bsize = 128,
183 .num_pmcs = 8,
184 .cpu_setup = __setup_cpu_power4,
185#ifdef CONFIG_OPROFILE
186 .oprofile_cpu_type = "ppc64/power4",
187 .oprofile_model = &op_model_power4,
188#endif
189 },
190 { /* PPC970 */
191 .pvr_mask = 0xffff0000,
192 .pvr_value = 0x00390000,
193 .cpu_name = "PPC970",
194 .cpu_features = CPU_FTRS_PPC970,
195 .cpu_user_features = COMMON_USER_PPC64 |
196 PPC_FEATURE_HAS_ALTIVEC_COMP,
197 .icache_bsize = 128,
198 .dcache_bsize = 128,
199 .num_pmcs = 8,
200 .cpu_setup = __setup_cpu_ppc970,
201#ifdef CONFIG_OPROFILE
202 .oprofile_cpu_type = "ppc64/970",
203 .oprofile_model = &op_model_power4,
204#endif
205 },
206#endif /* CONFIG_PPC64 */
207#if defined(CONFIG_PPC64) || defined(CONFIG_POWER4)
208 { /* PPC970FX */
209 .pvr_mask = 0xffff0000,
210 .pvr_value = 0x003c0000,
211 .cpu_name = "PPC970FX",
212#ifdef CONFIG_PPC32
213 .cpu_features = CPU_FTRS_970_32,
214#else
215 .cpu_features = CPU_FTRS_PPC970,
216#endif
217 .cpu_user_features = COMMON_USER_PPC64 |
218 PPC_FEATURE_HAS_ALTIVEC_COMP,
219 .icache_bsize = 128,
220 .dcache_bsize = 128,
221 .num_pmcs = 8,
222 .cpu_setup = __setup_cpu_ppc970,
223#ifdef CONFIG_OPROFILE
224 .oprofile_cpu_type = "ppc64/970",
225 .oprofile_model = &op_model_power4,
226#endif
227 },
228#endif /* defined(CONFIG_PPC64) || defined(CONFIG_POWER4) */
229#ifdef CONFIG_PPC64
230 { /* PPC970MP */
231 .pvr_mask = 0xffff0000,
232 .pvr_value = 0x00440000,
233 .cpu_name = "PPC970MP",
234 .cpu_features = CPU_FTRS_PPC970,
235 .cpu_user_features = COMMON_USER_PPC64 |
236 PPC_FEATURE_HAS_ALTIVEC_COMP,
237 .icache_bsize = 128,
238 .dcache_bsize = 128,
239 .cpu_setup = __setup_cpu_ppc970,
240#ifdef CONFIG_OPROFILE
241 .oprofile_cpu_type = "ppc64/970",
242 .oprofile_model = &op_model_power4,
243#endif
244 },
245 { /* Power5 */
246 .pvr_mask = 0xffff0000,
247 .pvr_value = 0x003a0000,
248 .cpu_name = "POWER5 (gr)",
249 .cpu_features = CPU_FTRS_POWER5,
250 .cpu_user_features = COMMON_USER_PPC64,
251 .icache_bsize = 128,
252 .dcache_bsize = 128,
253 .num_pmcs = 6,
254 .cpu_setup = __setup_cpu_power4,
255#ifdef CONFIG_OPROFILE
256 .oprofile_cpu_type = "ppc64/power5",
257 .oprofile_model = &op_model_power4,
258#endif
259 },
260 { /* Power5 */
261 .pvr_mask = 0xffff0000,
262 .pvr_value = 0x003b0000,
263 .cpu_name = "POWER5 (gs)",
264 .cpu_features = CPU_FTRS_POWER5,
265 .cpu_user_features = COMMON_USER_PPC64,
266 .icache_bsize = 128,
267 .dcache_bsize = 128,
268 .num_pmcs = 6,
269 .cpu_setup = __setup_cpu_power4,
270#ifdef CONFIG_OPROFILE
271 .oprofile_cpu_type = "ppc64/power5",
272 .oprofile_model = &op_model_power4,
273#endif
274 },
275 { /* BE DD1.x */
276 .pvr_mask = 0xffff0000,
277 .pvr_value = 0x00700000,
278 .cpu_name = "Cell Broadband Engine",
279 .cpu_features = CPU_FTRS_CELL,
280 .cpu_user_features = COMMON_USER_PPC64 |
281 PPC_FEATURE_HAS_ALTIVEC_COMP,
282 .icache_bsize = 128,
283 .dcache_bsize = 128,
284 .cpu_setup = __setup_cpu_be,
285 },
286 { /* default match */
287 .pvr_mask = 0x00000000,
288 .pvr_value = 0x00000000,
289 .cpu_name = "POWER4 (compatible)",
290 .cpu_features = CPU_FTRS_COMPATIBLE,
291 .cpu_user_features = COMMON_USER_PPC64,
292 .icache_bsize = 128,
293 .dcache_bsize = 128,
294 .num_pmcs = 6,
295 .cpu_setup = __setup_cpu_power4,
296 }
297#endif /* CONFIG_PPC64 */
298#ifdef CONFIG_PPC32
299#if CLASSIC_PPC
300 { /* 601 */
301 .pvr_mask = 0xffff0000,
302 .pvr_value = 0x00010000,
303 .cpu_name = "601",
304 .cpu_features = CPU_FTRS_PPC601,
305 .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR |
306 PPC_FEATURE_UNIFIED_CACHE,
307 .icache_bsize = 32,
308 .dcache_bsize = 32,
309 },
310 { /* 603 */
311 .pvr_mask = 0xffff0000,
312 .pvr_value = 0x00030000,
313 .cpu_name = "603",
314 .cpu_features = CPU_FTRS_603,
315 .cpu_user_features = COMMON_USER,
316 .icache_bsize = 32,
317 .dcache_bsize = 32,
318 .cpu_setup = __setup_cpu_603
319 },
320 { /* 603e */
321 .pvr_mask = 0xffff0000,
322 .pvr_value = 0x00060000,
323 .cpu_name = "603e",
324 .cpu_features = CPU_FTRS_603,
325 .cpu_user_features = COMMON_USER,
326 .icache_bsize = 32,
327 .dcache_bsize = 32,
328 .cpu_setup = __setup_cpu_603
329 },
330 { /* 603ev */
331 .pvr_mask = 0xffff0000,
332 .pvr_value = 0x00070000,
333 .cpu_name = "603ev",
334 .cpu_features = CPU_FTRS_603,
335 .cpu_user_features = COMMON_USER,
336 .icache_bsize = 32,
337 .dcache_bsize = 32,
338 .cpu_setup = __setup_cpu_603
339 },
340 { /* 604 */
341 .pvr_mask = 0xffff0000,
342 .pvr_value = 0x00040000,
343 .cpu_name = "604",
344 .cpu_features = CPU_FTRS_604,
345 .cpu_user_features = COMMON_USER,
346 .icache_bsize = 32,
347 .dcache_bsize = 32,
348 .num_pmcs = 2,
349 .cpu_setup = __setup_cpu_604
350 },
351 { /* 604e */
352 .pvr_mask = 0xfffff000,
353 .pvr_value = 0x00090000,
354 .cpu_name = "604e",
355 .cpu_features = CPU_FTRS_604,
356 .cpu_user_features = COMMON_USER,
357 .icache_bsize = 32,
358 .dcache_bsize = 32,
359 .num_pmcs = 4,
360 .cpu_setup = __setup_cpu_604
361 },
362 { /* 604r */
363 .pvr_mask = 0xffff0000,
364 .pvr_value = 0x00090000,
365 .cpu_name = "604r",
366 .cpu_features = CPU_FTRS_604,
367 .cpu_user_features = COMMON_USER,
368 .icache_bsize = 32,
369 .dcache_bsize = 32,
370 .num_pmcs = 4,
371 .cpu_setup = __setup_cpu_604
372 },
373 { /* 604ev */
374 .pvr_mask = 0xffff0000,
375 .pvr_value = 0x000a0000,
376 .cpu_name = "604ev",
377 .cpu_features = CPU_FTRS_604,
378 .cpu_user_features = COMMON_USER,
379 .icache_bsize = 32,
380 .dcache_bsize = 32,
381 .num_pmcs = 4,
382 .cpu_setup = __setup_cpu_604
383 },
384 { /* 740/750 (0x4202, don't support TAU ?) */
385 .pvr_mask = 0xffffffff,
386 .pvr_value = 0x00084202,
387 .cpu_name = "740/750",
388 .cpu_features = CPU_FTRS_740_NOTAU,
389 .cpu_user_features = COMMON_USER,
390 .icache_bsize = 32,
391 .dcache_bsize = 32,
392 .num_pmcs = 4,
393 .cpu_setup = __setup_cpu_750
394 },
395 { /* 750CX (80100 and 8010x?) */
396 .pvr_mask = 0xfffffff0,
397 .pvr_value = 0x00080100,
398 .cpu_name = "750CX",
399 .cpu_features = CPU_FTRS_750,
400 .cpu_user_features = COMMON_USER,
401 .icache_bsize = 32,
402 .dcache_bsize = 32,
403 .num_pmcs = 4,
404 .cpu_setup = __setup_cpu_750cx
405 },
406 { /* 750CX (82201 and 82202) */
407 .pvr_mask = 0xfffffff0,
408 .pvr_value = 0x00082200,
409 .cpu_name = "750CX",
410 .cpu_features = CPU_FTRS_750,
411 .cpu_user_features = COMMON_USER,
412 .icache_bsize = 32,
413 .dcache_bsize = 32,
414 .num_pmcs = 4,
415 .cpu_setup = __setup_cpu_750cx
416 },
417 { /* 750CXe (82214) */
418 .pvr_mask = 0xfffffff0,
419 .pvr_value = 0x00082210,
420 .cpu_name = "750CXe",
421 .cpu_features = CPU_FTRS_750,
422 .cpu_user_features = COMMON_USER,
423 .icache_bsize = 32,
424 .dcache_bsize = 32,
425 .num_pmcs = 4,
426 .cpu_setup = __setup_cpu_750cx
427 },
428 { /* 750CXe "Gekko" (83214) */
429 .pvr_mask = 0xffffffff,
430 .pvr_value = 0x00083214,
431 .cpu_name = "750CXe",
432 .cpu_features = CPU_FTRS_750,
433 .cpu_user_features = COMMON_USER,
434 .icache_bsize = 32,
435 .dcache_bsize = 32,
436 .num_pmcs = 4,
437 .cpu_setup = __setup_cpu_750cx
438 },
439 { /* 745/755 */
440 .pvr_mask = 0xfffff000,
441 .pvr_value = 0x00083000,
442 .cpu_name = "745/755",
443 .cpu_features = CPU_FTRS_750,
444 .cpu_user_features = COMMON_USER,
445 .icache_bsize = 32,
446 .dcache_bsize = 32,
447 .num_pmcs = 4,
448 .cpu_setup = __setup_cpu_750
449 },
450 { /* 750FX rev 1.x */
451 .pvr_mask = 0xffffff00,
452 .pvr_value = 0x70000100,
453 .cpu_name = "750FX",
454 .cpu_features = CPU_FTRS_750FX1,
455 .cpu_user_features = COMMON_USER,
456 .icache_bsize = 32,
457 .dcache_bsize = 32,
458 .num_pmcs = 4,
459 .cpu_setup = __setup_cpu_750
460 },
461 { /* 750FX rev 2.0 must disable HID0[DPM] */
462 .pvr_mask = 0xffffffff,
463 .pvr_value = 0x70000200,
464 .cpu_name = "750FX",
465 .cpu_features = CPU_FTRS_750FX2,
466 .cpu_user_features = COMMON_USER,
467 .icache_bsize = 32,
468 .dcache_bsize = 32,
469 .num_pmcs = 4,
470 .cpu_setup = __setup_cpu_750
471 },
472 { /* 750FX (All revs except 2.0) */
473 .pvr_mask = 0xffff0000,
474 .pvr_value = 0x70000000,
475 .cpu_name = "750FX",
476 .cpu_features = CPU_FTRS_750FX,
477 .cpu_user_features = COMMON_USER,
478 .icache_bsize = 32,
479 .dcache_bsize = 32,
480 .num_pmcs = 4,
481 .cpu_setup = __setup_cpu_750fx
482 },
483 { /* 750GX */
484 .pvr_mask = 0xffff0000,
485 .pvr_value = 0x70020000,
486 .cpu_name = "750GX",
487 .cpu_features = CPU_FTRS_750GX,
488 .cpu_user_features = COMMON_USER,
489 .icache_bsize = 32,
490 .dcache_bsize = 32,
491 .num_pmcs = 4,
492 .cpu_setup = __setup_cpu_750fx
493 },
494 { /* 740/750 (L2CR bit need fixup for 740) */
495 .pvr_mask = 0xffff0000,
496 .pvr_value = 0x00080000,
497 .cpu_name = "740/750",
498 .cpu_features = CPU_FTRS_740,
499 .cpu_user_features = COMMON_USER,
500 .icache_bsize = 32,
501 .dcache_bsize = 32,
502 .num_pmcs = 4,
503 .cpu_setup = __setup_cpu_750
504 },
505 { /* 7400 rev 1.1 ? (no TAU) */
506 .pvr_mask = 0xffffffff,
507 .pvr_value = 0x000c1101,
508 .cpu_name = "7400 (1.1)",
509 .cpu_features = CPU_FTRS_7400_NOTAU,
510 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
511 .icache_bsize = 32,
512 .dcache_bsize = 32,
513 .num_pmcs = 4,
514 .cpu_setup = __setup_cpu_7400
515 },
516 { /* 7400 */
517 .pvr_mask = 0xffff0000,
518 .pvr_value = 0x000c0000,
519 .cpu_name = "7400",
520 .cpu_features = CPU_FTRS_7400,
521 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
522 .icache_bsize = 32,
523 .dcache_bsize = 32,
524 .num_pmcs = 4,
525 .cpu_setup = __setup_cpu_7400
526 },
527 { /* 7410 */
528 .pvr_mask = 0xffff0000,
529 .pvr_value = 0x800c0000,
530 .cpu_name = "7410",
531 .cpu_features = CPU_FTRS_7400,
532 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
533 .icache_bsize = 32,
534 .dcache_bsize = 32,
535 .num_pmcs = 4,
536 .cpu_setup = __setup_cpu_7410
537 },
538 { /* 7450 2.0 - no doze/nap */
539 .pvr_mask = 0xffffffff,
540 .pvr_value = 0x80000200,
541 .cpu_name = "7450",
542 .cpu_features = CPU_FTRS_7450_20,
543 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
544 .icache_bsize = 32,
545 .dcache_bsize = 32,
546 .num_pmcs = 6,
547 .cpu_setup = __setup_cpu_745x
548 },
549 { /* 7450 2.1 */
550 .pvr_mask = 0xffffffff,
551 .pvr_value = 0x80000201,
552 .cpu_name = "7450",
553 .cpu_features = CPU_FTRS_7450_21,
554 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
555 .icache_bsize = 32,
556 .dcache_bsize = 32,
557 .num_pmcs = 6,
558 .cpu_setup = __setup_cpu_745x
559 },
560 { /* 7450 2.3 and newer */
561 .pvr_mask = 0xffff0000,
562 .pvr_value = 0x80000000,
563 .cpu_name = "7450",
564 .cpu_features = CPU_FTRS_7450_23,
565 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
566 .icache_bsize = 32,
567 .dcache_bsize = 32,
568 .num_pmcs = 6,
569 .cpu_setup = __setup_cpu_745x
570 },
571 { /* 7455 rev 1.x */
572 .pvr_mask = 0xffffff00,
573 .pvr_value = 0x80010100,
574 .cpu_name = "7455",
575 .cpu_features = CPU_FTRS_7455_1,
576 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
577 .icache_bsize = 32,
578 .dcache_bsize = 32,
579 .num_pmcs = 6,
580 .cpu_setup = __setup_cpu_745x
581 },
582 { /* 7455 rev 2.0 */
583 .pvr_mask = 0xffffffff,
584 .pvr_value = 0x80010200,
585 .cpu_name = "7455",
586 .cpu_features = CPU_FTRS_7455_20,
587 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
588 .icache_bsize = 32,
589 .dcache_bsize = 32,
590 .num_pmcs = 6,
591 .cpu_setup = __setup_cpu_745x
592 },
593 { /* 7455 others */
594 .pvr_mask = 0xffff0000,
595 .pvr_value = 0x80010000,
596 .cpu_name = "7455",
597 .cpu_features = CPU_FTRS_7455,
598 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
599 .icache_bsize = 32,
600 .dcache_bsize = 32,
601 .num_pmcs = 6,
602 .cpu_setup = __setup_cpu_745x
603 },
604 { /* 7447/7457 Rev 1.0 */
605 .pvr_mask = 0xffffffff,
606 .pvr_value = 0x80020100,
607 .cpu_name = "7447/7457",
608 .cpu_features = CPU_FTRS_7447_10,
609 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
610 .icache_bsize = 32,
611 .dcache_bsize = 32,
612 .num_pmcs = 6,
613 .cpu_setup = __setup_cpu_745x
614 },
615 { /* 7447/7457 Rev 1.1 */
616 .pvr_mask = 0xffffffff,
617 .pvr_value = 0x80020101,
618 .cpu_name = "7447/7457",
619 .cpu_features = CPU_FTRS_7447_10,
620 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
621 .icache_bsize = 32,
622 .dcache_bsize = 32,
623 .num_pmcs = 6,
624 .cpu_setup = __setup_cpu_745x
625 },
626 { /* 7447/7457 Rev 1.2 and later */
627 .pvr_mask = 0xffff0000,
628 .pvr_value = 0x80020000,
629 .cpu_name = "7447/7457",
630 .cpu_features = CPU_FTRS_7447,
631 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
632 .icache_bsize = 32,
633 .dcache_bsize = 32,
634 .num_pmcs = 6,
635 .cpu_setup = __setup_cpu_745x
636 },
637 { /* 7447A */
638 .pvr_mask = 0xffff0000,
639 .pvr_value = 0x80030000,
640 .cpu_name = "7447A",
641 .cpu_features = CPU_FTRS_7447A,
642 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
643 .icache_bsize = 32,
644 .dcache_bsize = 32,
645 .num_pmcs = 6,
646 .cpu_setup = __setup_cpu_745x
647 },
648 { /* 7448 */
649 .pvr_mask = 0xffff0000,
650 .pvr_value = 0x80040000,
651 .cpu_name = "7448",
652 .cpu_features = CPU_FTRS_7447A,
653 .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP,
654 .icache_bsize = 32,
655 .dcache_bsize = 32,
656 .num_pmcs = 6,
657 .cpu_setup = __setup_cpu_745x
658 },
659 { /* 82xx (8240, 8245, 8260 are all 603e cores) */
660 .pvr_mask = 0x7fff0000,
661 .pvr_value = 0x00810000,
662 .cpu_name = "82xx",
663 .cpu_features = CPU_FTRS_82XX,
664 .cpu_user_features = COMMON_USER,
665 .icache_bsize = 32,
666 .dcache_bsize = 32,
667 .cpu_setup = __setup_cpu_603
668 },
669 { /* All G2_LE (603e core, plus some) have the same pvr */
670 .pvr_mask = 0x7fff0000,
671 .pvr_value = 0x00820000,
672 .cpu_name = "G2_LE",
673 .cpu_features = CPU_FTRS_G2_LE,
674 .cpu_user_features = COMMON_USER,
675 .icache_bsize = 32,
676 .dcache_bsize = 32,
677 .cpu_setup = __setup_cpu_603
678 },
679 { /* e300 (a 603e core, plus some) on 83xx */
680 .pvr_mask = 0x7fff0000,
681 .pvr_value = 0x00830000,
682 .cpu_name = "e300",
683 .cpu_features = CPU_FTRS_E300,
684 .cpu_user_features = COMMON_USER,
685 .icache_bsize = 32,
686 .dcache_bsize = 32,
687 .cpu_setup = __setup_cpu_603
688 },
689 { /* default match, we assume split I/D cache & TB (non-601)... */
690 .pvr_mask = 0x00000000,
691 .pvr_value = 0x00000000,
692 .cpu_name = "(generic PPC)",
693 .cpu_features = CPU_FTRS_CLASSIC32,
694 .cpu_user_features = COMMON_USER,
695 .icache_bsize = 32,
696 .dcache_bsize = 32,
697 },
698#endif /* CLASSIC_PPC */
699#ifdef CONFIG_8xx
700 { /* 8xx */
701 .pvr_mask = 0xffff0000,
702 .pvr_value = 0x00500000,
703 .cpu_name = "8xx",
704 /* CPU_FTR_MAYBE_CAN_DOZE is possible,
705 * if the 8xx code is there.... */
706 .cpu_features = CPU_FTRS_8XX,
707 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
708 .icache_bsize = 16,
709 .dcache_bsize = 16,
710 },
711#endif /* CONFIG_8xx */
712#ifdef CONFIG_40x
713 { /* 403GC */
714 .pvr_mask = 0xffffff00,
715 .pvr_value = 0x00200200,
716 .cpu_name = "403GC",
717 .cpu_features = CPU_FTRS_40X,
718 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
719 .icache_bsize = 16,
720 .dcache_bsize = 16,
721 },
722 { /* 403GCX */
723 .pvr_mask = 0xffffff00,
724 .pvr_value = 0x00201400,
725 .cpu_name = "403GCX",
726 .cpu_features = CPU_FTRS_40X,
727 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
728 .icache_bsize = 16,
729 .dcache_bsize = 16,
730 },
731 { /* 403G ?? */
732 .pvr_mask = 0xffff0000,
733 .pvr_value = 0x00200000,
734 .cpu_name = "403G ??",
735 .cpu_features = CPU_FTRS_40X,
736 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
737 .icache_bsize = 16,
738 .dcache_bsize = 16,
739 },
740 { /* 405GP */
741 .pvr_mask = 0xffff0000,
742 .pvr_value = 0x40110000,
743 .cpu_name = "405GP",
744 .cpu_features = CPU_FTRS_40X,
745 .cpu_user_features = PPC_FEATURE_32 |
746 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
747 .icache_bsize = 32,
748 .dcache_bsize = 32,
749 },
750 { /* STB 03xxx */
751 .pvr_mask = 0xffff0000,
752 .pvr_value = 0x40130000,
753 .cpu_name = "STB03xxx",
754 .cpu_features = CPU_FTRS_40X,
755 .cpu_user_features = PPC_FEATURE_32 |
756 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
757 .icache_bsize = 32,
758 .dcache_bsize = 32,
759 },
760 { /* STB 04xxx */
761 .pvr_mask = 0xffff0000,
762 .pvr_value = 0x41810000,
763 .cpu_name = "STB04xxx",
764 .cpu_features = CPU_FTRS_40X,
765 .cpu_user_features = PPC_FEATURE_32 |
766 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
767 .icache_bsize = 32,
768 .dcache_bsize = 32,
769 },
770 { /* NP405L */
771 .pvr_mask = 0xffff0000,
772 .pvr_value = 0x41610000,
773 .cpu_name = "NP405L",
774 .cpu_features = CPU_FTRS_40X,
775 .cpu_user_features = PPC_FEATURE_32 |
776 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
777 .icache_bsize = 32,
778 .dcache_bsize = 32,
779 },
780 { /* NP4GS3 */
781 .pvr_mask = 0xffff0000,
782 .pvr_value = 0x40B10000,
783 .cpu_name = "NP4GS3",
784 .cpu_features = CPU_FTRS_40X,
785 .cpu_user_features = PPC_FEATURE_32 |
786 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
787 .icache_bsize = 32,
788 .dcache_bsize = 32,
789 },
790 { /* NP405H */
791 .pvr_mask = 0xffff0000,
792 .pvr_value = 0x41410000,
793 .cpu_name = "NP405H",
794 .cpu_features = CPU_FTRS_40X,
795 .cpu_user_features = PPC_FEATURE_32 |
796 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
797 .icache_bsize = 32,
798 .dcache_bsize = 32,
799 },
800 { /* 405GPr */
801 .pvr_mask = 0xffff0000,
802 .pvr_value = 0x50910000,
803 .cpu_name = "405GPr",
804 .cpu_features = CPU_FTRS_40X,
805 .cpu_user_features = PPC_FEATURE_32 |
806 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
807 .icache_bsize = 32,
808 .dcache_bsize = 32,
809 },
810 { /* STBx25xx */
811 .pvr_mask = 0xffff0000,
812 .pvr_value = 0x51510000,
813 .cpu_name = "STBx25xx",
814 .cpu_features = CPU_FTRS_40X,
815 .cpu_user_features = PPC_FEATURE_32 |
816 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
817 .icache_bsize = 32,
818 .dcache_bsize = 32,
819 },
820 { /* 405LP */
821 .pvr_mask = 0xffff0000,
822 .pvr_value = 0x41F10000,
823 .cpu_name = "405LP",
824 .cpu_features = CPU_FTRS_40X,
825 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
826 .icache_bsize = 32,
827 .dcache_bsize = 32,
828 },
829 { /* Xilinx Virtex-II Pro */
830 .pvr_mask = 0xffff0000,
831 .pvr_value = 0x20010000,
832 .cpu_name = "Virtex-II Pro",
833 .cpu_features = CPU_FTRS_40X,
834 .cpu_user_features = PPC_FEATURE_32 |
835 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
836 .icache_bsize = 32,
837 .dcache_bsize = 32,
838 },
839 { /* 405EP */
840 .pvr_mask = 0xffff0000,
841 .pvr_value = 0x51210000,
842 .cpu_name = "405EP",
843 .cpu_features = CPU_FTRS_40X,
844 .cpu_user_features = PPC_FEATURE_32 |
845 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
846 .icache_bsize = 32,
847 .dcache_bsize = 32,
848 },
849
850#endif /* CONFIG_40x */
851#ifdef CONFIG_44x
852 {
853 .pvr_mask = 0xf0000fff,
854 .pvr_value = 0x40000850,
855 .cpu_name = "440EP Rev. A",
856 .cpu_features = CPU_FTRS_44X,
857 .cpu_user_features = COMMON_USER, /* 440EP has an FPU */
858 .icache_bsize = 32,
859 .dcache_bsize = 32,
860 },
861 {
862 .pvr_mask = 0xf0000fff,
863 .pvr_value = 0x400008d3,
864 .cpu_name = "440EP Rev. B",
865 .cpu_features = CPU_FTRS_44X,
866 .cpu_user_features = COMMON_USER, /* 440EP has an FPU */
867 .icache_bsize = 32,
868 .dcache_bsize = 32,
869 },
870 { /* 440GP Rev. B */
871 .pvr_mask = 0xf0000fff,
872 .pvr_value = 0x40000440,
873 .cpu_name = "440GP Rev. B",
874 .cpu_features = CPU_FTRS_44X,
875 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
876 .icache_bsize = 32,
877 .dcache_bsize = 32,
878 },
879 { /* 440GP Rev. C */
880 .pvr_mask = 0xf0000fff,
881 .pvr_value = 0x40000481,
882 .cpu_name = "440GP Rev. C",
883 .cpu_features = CPU_FTRS_44X,
884 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
885 .icache_bsize = 32,
886 .dcache_bsize = 32,
887 },
888 { /* 440GX Rev. A */
889 .pvr_mask = 0xf0000fff,
890 .pvr_value = 0x50000850,
891 .cpu_name = "440GX Rev. A",
892 .cpu_features = CPU_FTRS_44X,
893 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
894 .icache_bsize = 32,
895 .dcache_bsize = 32,
896 },
897 { /* 440GX Rev. B */
898 .pvr_mask = 0xf0000fff,
899 .pvr_value = 0x50000851,
900 .cpu_name = "440GX Rev. B",
901 .cpu_features = CPU_FTRS_44X,
902 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
903 .icache_bsize = 32,
904 .dcache_bsize = 32,
905 },
906 { /* 440GX Rev. C */
907 .pvr_mask = 0xf0000fff,
908 .pvr_value = 0x50000892,
909 .cpu_name = "440GX Rev. C",
910 .cpu_features = CPU_FTRS_44X,
911 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
912 .icache_bsize = 32,
913 .dcache_bsize = 32,
914 },
915 { /* 440GX Rev. F */
916 .pvr_mask = 0xf0000fff,
917 .pvr_value = 0x50000894,
918 .cpu_name = "440GX Rev. F",
919 .cpu_features = CPU_FTRS_44X,
920 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
921 .icache_bsize = 32,
922 .dcache_bsize = 32,
923 },
924 { /* 440SP Rev. A */
925 .pvr_mask = 0xff000fff,
926 .pvr_value = 0x53000891,
927 .cpu_name = "440SP Rev. A",
928 .cpu_features = CPU_FTRS_44X,
929 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
930 .icache_bsize = 32,
931 .dcache_bsize = 32,
932 },
933#endif /* CONFIG_44x */
934#ifdef CONFIG_FSL_BOOKE
935 { /* e200z5 */
936 .pvr_mask = 0xfff00000,
937 .pvr_value = 0x81000000,
938 .cpu_name = "e200z5",
939 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
940 .cpu_features = CPU_FTRS_E200,
941 .cpu_user_features = PPC_FEATURE_32 |
942 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
943 PPC_FEATURE_UNIFIED_CACHE,
944 .dcache_bsize = 32,
945 },
946 { /* e200z6 */
947 .pvr_mask = 0xfff00000,
948 .pvr_value = 0x81100000,
949 .cpu_name = "e200z6",
950 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
951 .cpu_features = CPU_FTRS_E200,
952 .cpu_user_features = PPC_FEATURE_32 |
953 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
954 PPC_FEATURE_HAS_EFP_SINGLE |
955 PPC_FEATURE_UNIFIED_CACHE,
956 .dcache_bsize = 32,
957 },
958 { /* e500 */
959 .pvr_mask = 0xffff0000,
960 .pvr_value = 0x80200000,
961 .cpu_name = "e500",
962 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
963 .cpu_features = CPU_FTRS_E500,
964 .cpu_user_features = PPC_FEATURE_32 |
965 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
966 PPC_FEATURE_HAS_EFP_SINGLE,
967 .icache_bsize = 32,
968 .dcache_bsize = 32,
969 .num_pmcs = 4,
970 },
971 { /* e500v2 */
972 .pvr_mask = 0xffff0000,
973 .pvr_value = 0x80210000,
974 .cpu_name = "e500v2",
975 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
976 .cpu_features = CPU_FTRS_E500_2,
977 .cpu_user_features = PPC_FEATURE_32 |
978 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
979 PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
980 .icache_bsize = 32,
981 .dcache_bsize = 32,
982 .num_pmcs = 4,
983 },
984#endif
985#if !CLASSIC_PPC
986 { /* default match */
987 .pvr_mask = 0x00000000,
988 .pvr_value = 0x00000000,
989 .cpu_name = "(generic PPC)",
990 .cpu_features = CPU_FTRS_GENERIC_32,
991 .cpu_user_features = PPC_FEATURE_32,
992 .icache_bsize = 32,
993 .dcache_bsize = 32,
994 }
995#endif /* !CLASSIC_PPC */
996#endif /* CONFIG_PPC32 */
997};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-24 18:18:58 -0500