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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2013-09-05 02:43:30 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2013-09-05 02:43:30 -0400
commit91c2beb56b3ab5cf91fe04ddaeb69b90a22b5d36 (patch)
tree86dbad225295d8a63048da48728381614c10e1a2 /arch/powerpc/include
parent83c93e2bdfe33694032cc6d74e956755dd62e551 (diff)
parentf2110cb961200e5c382e9d0878ded015109b5dd6 (diff)
Merge remote-tracking branch 'agust/next' into next
From Anatolij: << There are cleanups for some mpc5121 specific drivers and DTS files in preparation to switch mpc5121 clock support to a clock driver based on common clock framework. Additionally Sebastian fixed the mpc52xx PIC driver so that it builds when using older gcc versions. >>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/mpc5121.h18
1 files changed, 2 insertions, 16 deletions
diff --git a/arch/powerpc/include/asm/mpc5121.h b/arch/powerpc/include/asm/mpc5121.h
index 8ae133eaf9fa..887d3d6133e3 100644
--- a/arch/powerpc/include/asm/mpc5121.h
+++ b/arch/powerpc/include/asm/mpc5121.h
@@ -32,25 +32,11 @@ struct mpc512x_ccm {
32 u32 scfr2; /* System Clock Frequency Register 2 */ 32 u32 scfr2; /* System Clock Frequency Register 2 */
33 u32 scfr2s; /* System Clock Frequency Shadow Register 2 */ 33 u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
34 u32 bcr; /* Bread Crumb Register */ 34 u32 bcr; /* Bread Crumb Register */
35 u32 p0ccr; /* PSC0 Clock Control Register */ 35 u32 psc_ccr[12]; /* PSC Clock Control Registers */
36 u32 p1ccr; /* PSC1 CCR */
37 u32 p2ccr; /* PSC2 CCR */
38 u32 p3ccr; /* PSC3 CCR */
39 u32 p4ccr; /* PSC4 CCR */
40 u32 p5ccr; /* PSC5 CCR */
41 u32 p6ccr; /* PSC6 CCR */
42 u32 p7ccr; /* PSC7 CCR */
43 u32 p8ccr; /* PSC8 CCR */
44 u32 p9ccr; /* PSC9 CCR */
45 u32 p10ccr; /* PSC10 CCR */
46 u32 p11ccr; /* PSC11 CCR */
47 u32 spccr; /* SPDIF Clock Control Register */ 36 u32 spccr; /* SPDIF Clock Control Register */
48 u32 cccr; /* CFM Clock Control Register */ 37 u32 cccr; /* CFM Clock Control Register */
49 u32 dccr; /* DIU Clock Control Register */ 38 u32 dccr; /* DIU Clock Control Register */
50 u32 m1ccr; /* MSCAN1 CCR */ 39 u32 mscan_ccr[4]; /* MSCAN Clock Control Registers */
51 u32 m2ccr; /* MSCAN2 CCR */
52 u32 m3ccr; /* MSCAN3 CCR */
53 u32 m4ccr; /* MSCAN4 CCR */
54 u8 res[0x98]; /* Reserved */ 40 u8 res[0x98]; /* Reserved */
55}; 41};
56 42