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authorLinus Torvalds <torvalds@linux-foundation.org>2015-04-16 14:53:32 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-04-16 14:53:32 -0400
commitd19d5efd8c8840aa4f38a6dfbfe500d8cc27de46 (patch)
tree2e2f4f57de790c7de2ccd6d1afbec8695b2c7a46 /arch/powerpc/include
parent34c9a0ffc75ad25b6a60f61e27c4a4b1189b8085 (diff)
parent2fe0753d49402aee325cc39c476b46fd51a8afec (diff)
Merge tag 'powerpc-4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux
Pull powerpc updates from Michael Ellerman: - Numerous minor fixes, cleanups etc. - More EEH work from Gavin to remove its dependency on device_nodes. - Memory hotplug implemented entirely in the kernel from Nathan Fontenot. - Removal of redundant CONFIG_PPC_OF by Kevin Hao. - Rewrite of VPHN parsing logic & tests from Greg Kurz. - A fix from Nish Aravamudan to reduce memory usage by clamping nodes_possible_map. - Support for pstore on powernv from Hari Bathini. - Removal of old powerpc specific byte swap routines by David Gibson. - Fix from Vasant Hegde to prevent the flash driver telling you it was flashing your firmware when it wasn't. - Patch from Ben Herrenschmidt to add an OPAL heartbeat driver. - Fix for an oops causing get/put_cpu_var() imbalance in perf by Jan Stancek. - Some fixes for migration from Tyrel Datwyler. - A new syscall to switch the cpu endian by Michael Ellerman. - Large series from Wei Yang to implement SRIOV, reviewed and acked by Bjorn. - A fix for the OPAL sensor driver from Cédric Le Goater. - Fixes to get STRICT_MM_TYPECHECKS building again by Michael Ellerman. - Large series from Daniel Axtens to make our PCI hooks per PHB rather than per machine. - Small patch from Sam Bobroff to explicitly abort non-suspended transactions on syscalls, plus a test to exercise it. - Numerous reworks and fixes for the 24x7 PMU from Sukadev Bhattiprolu. - Small patch to enable the hard lockup detector from Anton Blanchard. - Fix from Dave Olson for missing L2 cache information on some CPUs. - Some fixes from Michael Ellerman to get Cell machines booting again. - Freescale updates from Scott: Highlights include BMan device tree nodes, an MSI erratum workaround, a couple minor performance improvements, config updates, and misc fixes/cleanup. * tag 'powerpc-4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mpe/linux: (196 commits) powerpc/powermac: Fix build error seen with powermac smp builds powerpc/pseries: Fix compile of memory hotplug without CONFIG_MEMORY_HOTREMOVE powerpc: Remove PPC32 code from pseries specific find_and_init_phbs() powerpc/cell: Fix iommu breakage caused by controller_ops change powerpc/eeh: Fix crash in eeh_add_device_early() on Cell powerpc/perf: Cap 64bit userspace backtraces to PERF_MAX_STACK_DEPTH powerpc/perf/hv-24x7: Fail 24x7 initcall if create_events_from_catalog() fails powerpc/pseries: Correct memory hotplug locking powerpc: Fix missing L2 cache size in /sys/devices/system/cpu powerpc: Add ppc64 hard lockup detector support oprofile: Disable oprofile NMI timer on ppc64 powerpc/perf/hv-24x7: Add missing put_cpu_var() powerpc/perf/hv-24x7: Break up single_24x7_request powerpc/perf/hv-24x7: Define update_event_count() powerpc/perf/hv-24x7: Whitespace cleanup powerpc/perf/hv-24x7: Define add_event_to_24x7_request() powerpc/perf/hv-24x7: Rename hv_24x7_event_update powerpc/perf/hv-24x7: Move debug prints to separate function powerpc/perf/hv-24x7: Drop event_24x7_request() powerpc/perf/hv-24x7: Use pr_devel() to log message ... Conflicts: tools/testing/selftests/powerpc/Makefile tools/testing/selftests/powerpc/tm/Makefile
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/Kbuild4
-rw-r--r--arch/powerpc/include/asm/cache.h3
-rw-r--r--arch/powerpc/include/asm/cputable.h8
-rw-r--r--arch/powerpc/include/asm/dbdma.h12
-rw-r--r--arch/powerpc/include/asm/dcr-native.h2
-rw-r--r--arch/powerpc/include/asm/device.h6
-rw-r--r--arch/powerpc/include/asm/div64.h1
-rw-r--r--arch/powerpc/include/asm/dma-mapping.h4
-rw-r--r--arch/powerpc/include/asm/eeh.h29
-rw-r--r--arch/powerpc/include/asm/firmware.h10
-rw-r--r--arch/powerpc/include/asm/iommu.h6
-rw-r--r--arch/powerpc/include/asm/irq_regs.h2
-rw-r--r--arch/powerpc/include/asm/kvm_book3s_64.h16
-rw-r--r--arch/powerpc/include/asm/kvm_host.h2
-rw-r--r--arch/powerpc/include/asm/local64.h1
-rw-r--r--arch/powerpc/include/asm/machdep.h19
-rw-r--r--arch/powerpc/include/asm/mmu-hash64.h1
-rw-r--r--arch/powerpc/include/asm/mpc85xx.h1
-rw-r--r--arch/powerpc/include/asm/mpic.h17
-rw-r--r--arch/powerpc/include/asm/nmi.h4
-rw-r--r--arch/powerpc/include/asm/nvram.h50
-rw-r--r--arch/powerpc/include/asm/opal-api.h735
-rw-r--r--arch/powerpc/include/asm/opal.h770
-rw-r--r--arch/powerpc/include/asm/paca.h4
-rw-r--r--arch/powerpc/include/asm/pci-bridge.h60
-rw-r--r--arch/powerpc/include/asm/pci.h2
-rw-r--r--arch/powerpc/include/asm/ppc-pci.h8
-rw-r--r--arch/powerpc/include/asm/ppc_asm.h192
-rw-r--r--arch/powerpc/include/asm/rtas.h33
-rw-r--r--arch/powerpc/include/asm/setup.h1
-rw-r--r--arch/powerpc/include/asm/smp.h5
-rw-r--r--arch/powerpc/include/asm/swab.h26
-rw-r--r--arch/powerpc/include/asm/systbl.h1
-rw-r--r--arch/powerpc/include/asm/ucc_slow.h13
-rw-r--r--arch/powerpc/include/asm/unistd.h2
-rw-r--r--arch/powerpc/include/asm/vga.h4
-rw-r--r--arch/powerpc/include/asm/xics.h2
-rw-r--r--arch/powerpc/include/uapi/asm/ptrace.h2
-rw-r--r--arch/powerpc/include/uapi/asm/tm.h2
-rw-r--r--arch/powerpc/include/uapi/asm/unistd.h1
40 files changed, 1060 insertions, 1001 deletions
diff --git a/arch/powerpc/include/asm/Kbuild b/arch/powerpc/include/asm/Kbuild
index 382b28e364dc..4b87205c230c 100644
--- a/arch/powerpc/include/asm/Kbuild
+++ b/arch/powerpc/include/asm/Kbuild
@@ -1,6 +1,8 @@
1
2generic-y += clkdev.h 1generic-y += clkdev.h
2generic-y += div64.h
3generic-y += irq_regs.h
3generic-y += irq_work.h 4generic-y += irq_work.h
5generic-y += local64.h
4generic-y += mcs_spinlock.h 6generic-y += mcs_spinlock.h
5generic-y += preempt.h 7generic-y += preempt.h
6generic-y += rwsem.h 8generic-y += rwsem.h
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 34a05a1a990b..0dc42c5082b7 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -76,9 +76,6 @@ extern void _set_L3CR(unsigned long);
76#define _set_L3CR(val) do { } while(0) 76#define _set_L3CR(val) do { } while(0)
77#endif 77#endif
78 78
79extern void cacheable_memzero(void *p, unsigned int nb);
80extern void *cacheable_memcpy(void *, const void *, unsigned int);
81
82#endif /* !__ASSEMBLY__ */ 79#endif /* !__ASSEMBLY__ */
83#endif /* __KERNEL__ */ 80#endif /* __KERNEL__ */
84#endif /* _ASM_POWERPC_CACHE_H */ 81#endif /* _ASM_POWERPC_CACHE_H */
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index 5cf5a6d10685..6367b8347dad 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -100,7 +100,7 @@ struct cpu_spec {
100 /* 100 /*
101 * Processor specific routine to flush tlbs. 101 * Processor specific routine to flush tlbs.
102 */ 102 */
103 void (*flush_tlb)(unsigned long inval_selector); 103 void (*flush_tlb)(unsigned int action);
104 104
105}; 105};
106 106
@@ -114,6 +114,12 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
114 114
115extern const char *powerpc_base_platform; 115extern const char *powerpc_base_platform;
116 116
117/* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
118enum {
119 TLB_INVAL_SCOPE_GLOBAL = 0, /* invalidate all TLBs */
120 TLB_INVAL_SCOPE_LPID = 1, /* invalidate TLBs for current LPID */
121};
122
117#endif /* __ASSEMBLY__ */ 123#endif /* __ASSEMBLY__ */
118 124
119/* CPU kernel features */ 125/* CPU kernel features */
diff --git a/arch/powerpc/include/asm/dbdma.h b/arch/powerpc/include/asm/dbdma.h
index e23f07e73cb3..6c69836b4ec2 100644
--- a/arch/powerpc/include/asm/dbdma.h
+++ b/arch/powerpc/include/asm/dbdma.h
@@ -42,12 +42,12 @@ struct dbdma_regs {
42 * DBDMA command structure. These fields are all little-endian! 42 * DBDMA command structure. These fields are all little-endian!
43 */ 43 */
44struct dbdma_cmd { 44struct dbdma_cmd {
45 unsigned short req_count; /* requested byte transfer count */ 45 __le16 req_count; /* requested byte transfer count */
46 unsigned short command; /* command word (has bit-fields) */ 46 __le16 command; /* command word (has bit-fields) */
47 unsigned int phy_addr; /* physical data address */ 47 __le32 phy_addr; /* physical data address */
48 unsigned int cmd_dep; /* command-dependent field */ 48 __le32 cmd_dep; /* command-dependent field */
49 unsigned short res_count; /* residual count after completion */ 49 __le16 res_count; /* residual count after completion */
50 unsigned short xfer_status; /* transfer status */ 50 __le16 xfer_status; /* transfer status */
51}; 51};
52 52
53/* DBDMA command values in command field */ 53/* DBDMA command values in command field */
diff --git a/arch/powerpc/include/asm/dcr-native.h b/arch/powerpc/include/asm/dcr-native.h
index 7d2e6235726d..4efc11dacb98 100644
--- a/arch/powerpc/include/asm/dcr-native.h
+++ b/arch/powerpc/include/asm/dcr-native.h
@@ -31,7 +31,7 @@ typedef struct {
31 31
32static inline bool dcr_map_ok_native(dcr_host_native_t host) 32static inline bool dcr_map_ok_native(dcr_host_native_t host)
33{ 33{
34 return 1; 34 return true;
35} 35}
36 36
37#define dcr_map_native(dev, dcr_n, dcr_c) \ 37#define dcr_map_native(dev, dcr_n, dcr_c) \
diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h
index 38faeded7d59..9f1371bab5fc 100644
--- a/arch/powerpc/include/asm/device.h
+++ b/arch/powerpc/include/asm/device.h
@@ -8,6 +8,9 @@
8 8
9struct dma_map_ops; 9struct dma_map_ops;
10struct device_node; 10struct device_node;
11#ifdef CONFIG_PPC64
12struct pci_dn;
13#endif
11 14
12/* 15/*
13 * Arch extensions to struct device. 16 * Arch extensions to struct device.
@@ -34,6 +37,9 @@ struct dev_archdata {
34#ifdef CONFIG_SWIOTLB 37#ifdef CONFIG_SWIOTLB
35 dma_addr_t max_direct_dma_addr; 38 dma_addr_t max_direct_dma_addr;
36#endif 39#endif
40#ifdef CONFIG_PPC64
41 struct pci_dn *pci_data;
42#endif
37#ifdef CONFIG_EEH 43#ifdef CONFIG_EEH
38 struct eeh_dev *edev; 44 struct eeh_dev *edev;
39#endif 45#endif
diff --git a/arch/powerpc/include/asm/div64.h b/arch/powerpc/include/asm/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/arch/powerpc/include/asm/div64.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/div64.h>
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h
index 894d538f3567..9103687b0436 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -191,11 +191,11 @@ static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
191 struct dev_archdata *sd = &dev->archdata; 191 struct dev_archdata *sd = &dev->archdata;
192 192
193 if (sd->max_direct_dma_addr && addr + size > sd->max_direct_dma_addr) 193 if (sd->max_direct_dma_addr && addr + size > sd->max_direct_dma_addr)
194 return 0; 194 return false;
195#endif 195#endif
196 196
197 if (!dev->dma_mask) 197 if (!dev->dma_mask)
198 return 0; 198 return false;
199 199
200 return addr + size - 1 <= *dev->dma_mask; 200 return addr + size - 1 <= *dev->dma_mask;
201} 201}
diff --git a/arch/powerpc/include/asm/eeh.h b/arch/powerpc/include/asm/eeh.h
index 55abfd09e47f..a52db28ecc1e 100644
--- a/arch/powerpc/include/asm/eeh.h
+++ b/arch/powerpc/include/asm/eeh.h
@@ -29,7 +29,7 @@
29 29
30struct pci_dev; 30struct pci_dev;
31struct pci_bus; 31struct pci_bus;
32struct device_node; 32struct pci_dn;
33 33
34#ifdef CONFIG_EEH 34#ifdef CONFIG_EEH
35 35
@@ -136,14 +136,14 @@ struct eeh_dev {
136 struct eeh_pe *pe; /* Associated PE */ 136 struct eeh_pe *pe; /* Associated PE */
137 struct list_head list; /* Form link list in the PE */ 137 struct list_head list; /* Form link list in the PE */
138 struct pci_controller *phb; /* Associated PHB */ 138 struct pci_controller *phb; /* Associated PHB */
139 struct device_node *dn; /* Associated device node */ 139 struct pci_dn *pdn; /* Associated PCI device node */
140 struct pci_dev *pdev; /* Associated PCI device */ 140 struct pci_dev *pdev; /* Associated PCI device */
141 struct pci_bus *bus; /* PCI bus for partial hotplug */ 141 struct pci_bus *bus; /* PCI bus for partial hotplug */
142}; 142};
143 143
144static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev) 144static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
145{ 145{
146 return edev ? edev->dn : NULL; 146 return edev ? edev->pdn : NULL;
147} 147}
148 148
149static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev) 149static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
@@ -200,8 +200,7 @@ struct eeh_ops {
200 char *name; 200 char *name;
201 int (*init)(void); 201 int (*init)(void);
202 int (*post_init)(void); 202 int (*post_init)(void);
203 void* (*of_probe)(struct device_node *dn, void *flag); 203 void* (*probe)(struct pci_dn *pdn, void *data);
204 int (*dev_probe)(struct pci_dev *dev, void *flag);
205 int (*set_option)(struct eeh_pe *pe, int option); 204 int (*set_option)(struct eeh_pe *pe, int option);
206 int (*get_pe_addr)(struct eeh_pe *pe); 205 int (*get_pe_addr)(struct eeh_pe *pe);
207 int (*get_state)(struct eeh_pe *pe, int *state); 206 int (*get_state)(struct eeh_pe *pe, int *state);
@@ -211,10 +210,10 @@ struct eeh_ops {
211 int (*configure_bridge)(struct eeh_pe *pe); 210 int (*configure_bridge)(struct eeh_pe *pe);
212 int (*err_inject)(struct eeh_pe *pe, int type, int func, 211 int (*err_inject)(struct eeh_pe *pe, int type, int func,
213 unsigned long addr, unsigned long mask); 212 unsigned long addr, unsigned long mask);
214 int (*read_config)(struct device_node *dn, int where, int size, u32 *val); 213 int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val);
215 int (*write_config)(struct device_node *dn, int where, int size, u32 val); 214 int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val);
216 int (*next_error)(struct eeh_pe **pe); 215 int (*next_error)(struct eeh_pe **pe);
217 int (*restore_config)(struct device_node *dn); 216 int (*restore_config)(struct pci_dn *pdn);
218}; 217};
219 218
220extern int eeh_subsystem_flags; 219extern int eeh_subsystem_flags;
@@ -272,7 +271,7 @@ void eeh_pe_restore_bars(struct eeh_pe *pe);
272const char *eeh_pe_loc_get(struct eeh_pe *pe); 271const char *eeh_pe_loc_get(struct eeh_pe *pe);
273struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe); 272struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
274 273
275void *eeh_dev_init(struct device_node *dn, void *data); 274void *eeh_dev_init(struct pci_dn *pdn, void *data);
276void eeh_dev_phb_init_dynamic(struct pci_controller *phb); 275void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
277int eeh_init(void); 276int eeh_init(void);
278int __init eeh_ops_register(struct eeh_ops *ops); 277int __init eeh_ops_register(struct eeh_ops *ops);
@@ -280,8 +279,8 @@ int __exit eeh_ops_unregister(const char *name);
280int eeh_check_failure(const volatile void __iomem *token); 279int eeh_check_failure(const volatile void __iomem *token);
281int eeh_dev_check_failure(struct eeh_dev *edev); 280int eeh_dev_check_failure(struct eeh_dev *edev);
282void eeh_addr_cache_build(void); 281void eeh_addr_cache_build(void);
283void eeh_add_device_early(struct device_node *); 282void eeh_add_device_early(struct pci_dn *);
284void eeh_add_device_tree_early(struct device_node *); 283void eeh_add_device_tree_early(struct pci_dn *);
285void eeh_add_device_late(struct pci_dev *); 284void eeh_add_device_late(struct pci_dev *);
286void eeh_add_device_tree_late(struct pci_bus *); 285void eeh_add_device_tree_late(struct pci_bus *);
287void eeh_add_sysfs_files(struct pci_bus *); 286void eeh_add_sysfs_files(struct pci_bus *);
@@ -323,7 +322,7 @@ static inline int eeh_init(void)
323 return 0; 322 return 0;
324} 323}
325 324
326static inline void *eeh_dev_init(struct device_node *dn, void *data) 325static inline void *eeh_dev_init(struct pci_dn *pdn, void *data)
327{ 326{
328 return NULL; 327 return NULL;
329} 328}
@@ -339,9 +338,9 @@ static inline int eeh_check_failure(const volatile void __iomem *token)
339 338
340static inline void eeh_addr_cache_build(void) { } 339static inline void eeh_addr_cache_build(void) { }
341 340
342static inline void eeh_add_device_early(struct device_node *dn) { } 341static inline void eeh_add_device_early(struct pci_dn *pdn) { }
343 342
344static inline void eeh_add_device_tree_early(struct device_node *dn) { } 343static inline void eeh_add_device_tree_early(struct pci_dn *pdn) { }
345 344
346static inline void eeh_add_device_late(struct pci_dev *dev) { } 345static inline void eeh_add_device_late(struct pci_dev *dev) { }
347 346
diff --git a/arch/powerpc/include/asm/firmware.h b/arch/powerpc/include/asm/firmware.h
index 681bc0314b6b..e05808a328db 100644
--- a/arch/powerpc/include/asm/firmware.h
+++ b/arch/powerpc/include/asm/firmware.h
@@ -42,7 +42,7 @@
42#define FW_FEATURE_SPLPAR ASM_CONST(0x0000000000100000) 42#define FW_FEATURE_SPLPAR ASM_CONST(0x0000000000100000)
43#define FW_FEATURE_LPAR ASM_CONST(0x0000000000400000) 43#define FW_FEATURE_LPAR ASM_CONST(0x0000000000400000)
44#define FW_FEATURE_PS3_LV1 ASM_CONST(0x0000000000800000) 44#define FW_FEATURE_PS3_LV1 ASM_CONST(0x0000000000800000)
45#define FW_FEATURE_BEAT ASM_CONST(0x0000000001000000) 45/* Free ASM_CONST(0x0000000001000000) */
46#define FW_FEATURE_CMO ASM_CONST(0x0000000002000000) 46#define FW_FEATURE_CMO ASM_CONST(0x0000000002000000)
47#define FW_FEATURE_VPHN ASM_CONST(0x0000000004000000) 47#define FW_FEATURE_VPHN ASM_CONST(0x0000000004000000)
48#define FW_FEATURE_XCMO ASM_CONST(0x0000000008000000) 48#define FW_FEATURE_XCMO ASM_CONST(0x0000000008000000)
@@ -75,8 +75,6 @@ enum {
75 FW_FEATURE_POWERNV_ALWAYS = 0, 75 FW_FEATURE_POWERNV_ALWAYS = 0,
76 FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1, 76 FW_FEATURE_PS3_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
77 FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1, 77 FW_FEATURE_PS3_ALWAYS = FW_FEATURE_LPAR | FW_FEATURE_PS3_LV1,
78 FW_FEATURE_CELLEB_POSSIBLE = FW_FEATURE_LPAR | FW_FEATURE_BEAT,
79 FW_FEATURE_CELLEB_ALWAYS = 0,
80 FW_FEATURE_NATIVE_POSSIBLE = 0, 78 FW_FEATURE_NATIVE_POSSIBLE = 0,
81 FW_FEATURE_NATIVE_ALWAYS = 0, 79 FW_FEATURE_NATIVE_ALWAYS = 0,
82 FW_FEATURE_POSSIBLE = 80 FW_FEATURE_POSSIBLE =
@@ -89,9 +87,6 @@ enum {
89#ifdef CONFIG_PPC_PS3 87#ifdef CONFIG_PPC_PS3
90 FW_FEATURE_PS3_POSSIBLE | 88 FW_FEATURE_PS3_POSSIBLE |
91#endif 89#endif
92#ifdef CONFIG_PPC_CELLEB
93 FW_FEATURE_CELLEB_POSSIBLE |
94#endif
95#ifdef CONFIG_PPC_NATIVE 90#ifdef CONFIG_PPC_NATIVE
96 FW_FEATURE_NATIVE_ALWAYS | 91 FW_FEATURE_NATIVE_ALWAYS |
97#endif 92#endif
@@ -106,9 +101,6 @@ enum {
106#ifdef CONFIG_PPC_PS3 101#ifdef CONFIG_PPC_PS3
107 FW_FEATURE_PS3_ALWAYS & 102 FW_FEATURE_PS3_ALWAYS &
108#endif 103#endif
109#ifdef CONFIG_PPC_CELLEB
110 FW_FEATURE_CELLEB_ALWAYS &
111#endif
112#ifdef CONFIG_PPC_NATIVE 104#ifdef CONFIG_PPC_NATIVE
113 FW_FEATURE_NATIVE_ALWAYS & 105 FW_FEATURE_NATIVE_ALWAYS &
114#endif 106#endif
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
index f1ea5972f6ec..1e27d6338565 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
@@ -29,6 +29,7 @@
29#include <linux/bitops.h> 29#include <linux/bitops.h>
30#include <asm/machdep.h> 30#include <asm/machdep.h>
31#include <asm/types.h> 31#include <asm/types.h>
32#include <asm/pci-bridge.h>
32 33
33#define IOMMU_PAGE_SHIFT_4K 12 34#define IOMMU_PAGE_SHIFT_4K 12
34#define IOMMU_PAGE_SIZE_4K (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K) 35#define IOMMU_PAGE_SIZE_4K (ASM_CONST(1) << IOMMU_PAGE_SHIFT_4K)
@@ -78,6 +79,9 @@ struct iommu_table {
78 struct iommu_group *it_group; 79 struct iommu_group *it_group;
79#endif 80#endif
80 void (*set_bypass)(struct iommu_table *tbl, bool enable); 81 void (*set_bypass)(struct iommu_table *tbl, bool enable);
82#ifdef CONFIG_PPC_POWERNV
83 void *data;
84#endif
81}; 85};
82 86
83/* Pure 2^n version of get_order */ 87/* Pure 2^n version of get_order */
@@ -169,7 +173,7 @@ extern void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
169 struct dma_attrs *attrs); 173 struct dma_attrs *attrs);
170 174
171extern void iommu_init_early_pSeries(void); 175extern void iommu_init_early_pSeries(void);
172extern void iommu_init_early_dart(void); 176extern void iommu_init_early_dart(struct pci_controller_ops *controller_ops);
173extern void iommu_init_early_pasemi(void); 177extern void iommu_init_early_pasemi(void);
174 178
175extern void alloc_dart_table(void); 179extern void alloc_dart_table(void);
diff --git a/arch/powerpc/include/asm/irq_regs.h b/arch/powerpc/include/asm/irq_regs.h
deleted file mode 100644
index ba94b51a0a70..000000000000
--- a/arch/powerpc/include/asm/irq_regs.h
+++ /dev/null
@@ -1,2 +0,0 @@
1#include <asm-generic/irq_regs.h>
2
diff --git a/arch/powerpc/include/asm/kvm_book3s_64.h b/arch/powerpc/include/asm/kvm_book3s_64.h
index 2d81e202bdcc..14619a59ec09 100644
--- a/arch/powerpc/include/asm/kvm_book3s_64.h
+++ b/arch/powerpc/include/asm/kvm_book3s_64.h
@@ -290,11 +290,11 @@ static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing,
290 pte_t old_pte, new_pte = __pte(0); 290 pte_t old_pte, new_pte = __pte(0);
291 291
292 while (1) { 292 while (1) {
293 old_pte = pte_val(*ptep); 293 old_pte = *ptep;
294 /* 294 /*
295 * wait until _PAGE_BUSY is clear then set it atomically 295 * wait until _PAGE_BUSY is clear then set it atomically
296 */ 296 */
297 if (unlikely(old_pte & _PAGE_BUSY)) { 297 if (unlikely(pte_val(old_pte) & _PAGE_BUSY)) {
298 cpu_relax(); 298 cpu_relax();
299 continue; 299 continue;
300 } 300 }
@@ -305,16 +305,18 @@ static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing,
305 return __pte(0); 305 return __pte(0);
306#endif 306#endif
307 /* If pte is not present return None */ 307 /* If pte is not present return None */
308 if (unlikely(!(old_pte & _PAGE_PRESENT))) 308 if (unlikely(!(pte_val(old_pte) & _PAGE_PRESENT)))
309 return __pte(0); 309 return __pte(0);
310 310
311 new_pte = pte_mkyoung(old_pte); 311 new_pte = pte_mkyoung(old_pte);
312 if (writing && pte_write(old_pte)) 312 if (writing && pte_write(old_pte))
313 new_pte = pte_mkdirty(new_pte); 313 new_pte = pte_mkdirty(new_pte);
314 314
315 if (old_pte == __cmpxchg_u64((unsigned long *)ptep, old_pte, 315 if (pte_val(old_pte) == __cmpxchg_u64((unsigned long *)ptep,
316 new_pte)) 316 pte_val(old_pte),
317 pte_val(new_pte))) {
317 break; 318 break;
319 }
318 } 320 }
319 return new_pte; 321 return new_pte;
320} 322}
@@ -335,7 +337,7 @@ static inline bool hpte_read_permission(unsigned long pp, unsigned long key)
335{ 337{
336 if (key) 338 if (key)
337 return PP_RWRX <= pp && pp <= PP_RXRX; 339 return PP_RWRX <= pp && pp <= PP_RXRX;
338 return 1; 340 return true;
339} 341}
340 342
341static inline bool hpte_write_permission(unsigned long pp, unsigned long key) 343static inline bool hpte_write_permission(unsigned long pp, unsigned long key)
@@ -373,7 +375,7 @@ static inline bool slot_is_aligned(struct kvm_memory_slot *memslot,
373 unsigned long mask = (pagesize >> PAGE_SHIFT) - 1; 375 unsigned long mask = (pagesize >> PAGE_SHIFT) - 1;
374 376
375 if (pagesize <= PAGE_SIZE) 377 if (pagesize <= PAGE_SIZE)
376 return 1; 378 return true;
377 return !(memslot->base_gfn & mask) && !(memslot->npages & mask); 379 return !(memslot->base_gfn & mask) && !(memslot->npages & mask);
378} 380}
379 381
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index 8ef05121d3cd..c610961720c7 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -585,7 +585,7 @@ struct kvm_vcpu_arch {
585 pgd_t *pgdir; 585 pgd_t *pgdir;
586 586
587 u8 io_gpr; /* GPR used as IO source/target */ 587 u8 io_gpr; /* GPR used as IO source/target */
588 u8 mmio_is_bigendian; 588 u8 mmio_host_swabbed;
589 u8 mmio_sign_extend; 589 u8 mmio_sign_extend;
590 u8 osi_needed; 590 u8 osi_needed;
591 u8 osi_enabled; 591 u8 osi_enabled;
diff --git a/arch/powerpc/include/asm/local64.h b/arch/powerpc/include/asm/local64.h
deleted file mode 100644
index 36c93b5cc239..000000000000
--- a/arch/powerpc/include/asm/local64.h
+++ /dev/null
@@ -1 +0,0 @@
1#include <asm-generic/local64.h>
diff --git a/arch/powerpc/include/asm/machdep.h b/arch/powerpc/include/asm/machdep.h
index c8175a3fe560..ef8899432ae7 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -103,9 +103,6 @@ struct machdep_calls {
103#endif 103#endif
104#endif /* CONFIG_PPC64 */ 104#endif /* CONFIG_PPC64 */
105 105
106 void (*pci_dma_dev_setup)(struct pci_dev *dev);
107 void (*pci_dma_bus_setup)(struct pci_bus *bus);
108
109 /* Platform set_dma_mask and dma_get_required_mask overrides */ 106 /* Platform set_dma_mask and dma_get_required_mask overrides */
110 int (*dma_set_mask)(struct device *dev, u64 dma_mask); 107 int (*dma_set_mask)(struct device *dev, u64 dma_mask);
111 u64 (*dma_get_required_mask)(struct device *dev); 108 u64 (*dma_get_required_mask)(struct device *dev);
@@ -125,9 +122,8 @@ struct machdep_calls {
125 unsigned int (*get_irq)(void); 122 unsigned int (*get_irq)(void);
126 123
127 /* PCI stuff */ 124 /* PCI stuff */
128 /* Called after scanning the bus, before allocating resources */ 125 /* Called after allocating resources */
129 void (*pcibios_fixup)(void); 126 void (*pcibios_fixup)(void);
130 int (*pci_probe_mode)(struct pci_bus *);
131 void (*pci_irq_fixup)(struct pci_dev *dev); 127 void (*pci_irq_fixup)(struct pci_dev *dev);
132 int (*pcibios_root_bridge_prepare)(struct pci_host_bridge 128 int (*pcibios_root_bridge_prepare)(struct pci_host_bridge
133 *bridge); 129 *bridge);
@@ -237,18 +233,13 @@ struct machdep_calls {
237 /* Called for each PCI bus in the system when it's probed */ 233 /* Called for each PCI bus in the system when it's probed */
238 void (*pcibios_fixup_bus)(struct pci_bus *); 234 void (*pcibios_fixup_bus)(struct pci_bus *);
239 235
240 /* Called when pci_enable_device() is called. Returns 0 to
241 * allow assignment/enabling of the device. */
242 int (*pcibios_enable_device_hook)(struct pci_dev *);
243
244 /* Called after scan and before resource survey */ 236 /* Called after scan and before resource survey */
245 void (*pcibios_fixup_phb)(struct pci_controller *hose); 237 void (*pcibios_fixup_phb)(struct pci_controller *hose);
246 238
247 /* Called during PCI resource reassignment */ 239#ifdef CONFIG_PCI_IOV
248 resource_size_t (*pcibios_window_alignment)(struct pci_bus *, unsigned long type); 240 void (*pcibios_fixup_sriov)(struct pci_dev *pdev);
249 241 resource_size_t (*pcibios_iov_resource_alignment)(struct pci_dev *, int resno);
250 /* Reset the secondary bus of bridge */ 242#endif /* CONFIG_PCI_IOV */
251 void (*pcibios_reset_secondary_bus)(struct pci_dev *dev);
252 243
253 /* Called to shutdown machine specific hardware not already controlled 244 /* Called to shutdown machine specific hardware not already controlled
254 * by other drivers. 245 * by other drivers.
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
index 4f13c3ed7acf..1da6a81ce541 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
@@ -112,6 +112,7 @@
112#define TLBIEL_INVAL_SET_SHIFT 12 112#define TLBIEL_INVAL_SET_SHIFT 12
113 113
114#define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */ 114#define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
115#define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */
115 116
116#ifndef __ASSEMBLY__ 117#ifndef __ASSEMBLY__
117 118
diff --git a/arch/powerpc/include/asm/mpc85xx.h b/arch/powerpc/include/asm/mpc85xx.h
index 3bef74a9914b..213f3a81593d 100644
--- a/arch/powerpc/include/asm/mpc85xx.h
+++ b/arch/powerpc/include/asm/mpc85xx.h
@@ -61,6 +61,7 @@
61#define SVR_T4240 0x824000 61#define SVR_T4240 0x824000
62#define SVR_T4120 0x824001 62#define SVR_T4120 0x824001
63#define SVR_T4160 0x824100 63#define SVR_T4160 0x824100
64#define SVR_T4080 0x824102
64#define SVR_C291 0x850000 65#define SVR_C291 0x850000
65#define SVR_C292 0x850020 66#define SVR_C292 0x850020
66#define SVR_C293 0x850030 67#define SVR_C293 0x850030
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index 754f93d208fa..98697611e7b3 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -34,10 +34,6 @@
34#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff 34#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
35#define MPIC_GREG_GCONF_MCK 0x08000000 35#define MPIC_GREG_GCONF_MCK 0x08000000
36#define MPIC_GREG_GLOBAL_CONF_1 0x00030 36#define MPIC_GREG_GLOBAL_CONF_1 0x00030
37#define MPIC_GREG_GLOBAL_CONF_1_SIE 0x08000000
38#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK 0x70000000
39#define MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r) \
40 (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
41#define MPIC_GREG_VENDOR_0 0x00040 37#define MPIC_GREG_VENDOR_0 0x00040
42#define MPIC_GREG_VENDOR_1 0x00050 38#define MPIC_GREG_VENDOR_1 0x00050
43#define MPIC_GREG_VENDOR_2 0x00060 39#define MPIC_GREG_VENDOR_2 0x00060
@@ -396,14 +392,7 @@ extern struct bus_type mpic_subsys;
396#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */ 392#define MPIC_REGSET_TSI108 MPIC_REGSET(1) /* Tsi108/109 PIC */
397 393
398/* Get the version of primary MPIC */ 394/* Get the version of primary MPIC */
399#ifdef CONFIG_MPIC
400extern u32 fsl_mpic_primary_get_version(void); 395extern u32 fsl_mpic_primary_get_version(void);
401#else
402static inline u32 fsl_mpic_primary_get_version(void)
403{
404 return 0;
405}
406#endif
407 396
408/* Allocate the controller structure and setup the linux irq descs 397/* Allocate the controller structure and setup the linux irq descs
409 * for the range if interrupts passed in. No HW initialization is 398 * for the range if interrupts passed in. No HW initialization is
@@ -496,11 +485,5 @@ extern unsigned int mpic_get_coreint_irq(void);
496/* Fetch Machine Check interrupt from primary mpic */ 485/* Fetch Machine Check interrupt from primary mpic */
497extern unsigned int mpic_get_mcirq(void); 486extern unsigned int mpic_get_mcirq(void);
498 487
499/* Set the EPIC clock ratio */
500void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
501
502/* Enable/Disable EPIC serial interrupt mode */
503void mpic_set_serial_int(struct mpic *mpic, int enable);
504
505#endif /* __KERNEL__ */ 488#endif /* __KERNEL__ */
506#endif /* _ASM_POWERPC_MPIC_H */ 489#endif /* _ASM_POWERPC_MPIC_H */
diff --git a/arch/powerpc/include/asm/nmi.h b/arch/powerpc/include/asm/nmi.h
new file mode 100644
index 000000000000..ff1ccb375e60
--- /dev/null
+++ b/arch/powerpc/include/asm/nmi.h
@@ -0,0 +1,4 @@
1#ifndef _ASM_NMI_H
2#define _ASM_NMI_H
3
4#endif /* _ASM_NMI_H */
diff --git a/arch/powerpc/include/asm/nvram.h b/arch/powerpc/include/asm/nvram.h
index b0fe0fe4e626..09a518bb7c03 100644
--- a/arch/powerpc/include/asm/nvram.h
+++ b/arch/powerpc/include/asm/nvram.h
@@ -9,12 +9,43 @@
9#ifndef _ASM_POWERPC_NVRAM_H 9#ifndef _ASM_POWERPC_NVRAM_H
10#define _ASM_POWERPC_NVRAM_H 10#define _ASM_POWERPC_NVRAM_H
11 11
12 12#include <linux/types.h>
13#include <linux/errno.h> 13#include <linux/errno.h>
14#include <linux/list.h> 14#include <linux/list.h>
15#include <uapi/asm/nvram.h> 15#include <uapi/asm/nvram.h>
16 16
17/*
18 * Set oops header version to distinguish between old and new format header.
19 * lnx,oops-log partition max size is 4000, header version > 4000 will
20 * help in identifying new header.
21 */
22#define OOPS_HDR_VERSION 5000
23
24struct err_log_info {
25 __be32 error_type;
26 __be32 seq_num;
27};
28
29struct nvram_os_partition {
30 const char *name;
31 int req_size; /* desired size, in bytes */
32 int min_size; /* minimum acceptable size (0 means req_size) */
33 long size; /* size of data portion (excluding err_log_info) */
34 long index; /* offset of data portion of partition */
35 bool os_partition; /* partition initialized by OS, not FW */
36};
37
38struct oops_log_info {
39 __be16 version;
40 __be16 report_length;
41 __be64 timestamp;
42} __attribute__((packed));
43
44extern struct nvram_os_partition oops_log_partition;
45
17#ifdef CONFIG_PPC_PSERIES 46#ifdef CONFIG_PPC_PSERIES
47extern struct nvram_os_partition rtas_log_partition;
48
18extern int nvram_write_error_log(char * buff, int length, 49extern int nvram_write_error_log(char * buff, int length,
19 unsigned int err_type, unsigned int err_seq); 50 unsigned int err_type, unsigned int err_seq);
20extern int nvram_read_error_log(char * buff, int length, 51extern int nvram_read_error_log(char * buff, int length,
@@ -50,6 +81,23 @@ extern void pmac_xpram_write(int xpaddr, u8 data);
50/* Synchronize NVRAM */ 81/* Synchronize NVRAM */
51extern void nvram_sync(void); 82extern void nvram_sync(void);
52 83
84/* Initialize NVRAM OS partition */
85extern int __init nvram_init_os_partition(struct nvram_os_partition *part);
86
87/* Initialize NVRAM oops partition */
88extern void __init nvram_init_oops_partition(int rtas_partition_exists);
89
90/* Read a NVRAM partition */
91extern int nvram_read_partition(struct nvram_os_partition *part, char *buff,
92 int length, unsigned int *err_type,
93 unsigned int *error_log_cnt);
94
95/* Write to NVRAM OS partition */
96extern int nvram_write_os_partition(struct nvram_os_partition *part,
97 char *buff, int length,
98 unsigned int err_type,
99 unsigned int error_log_cnt);
100
53/* Determine NVRAM size */ 101/* Determine NVRAM size */
54extern ssize_t nvram_get_size(void); 102extern ssize_t nvram_get_size(void);
55 103
diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
new file mode 100644
index 000000000000..0321a909e663
--- /dev/null
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -0,0 +1,735 @@
1/*
2 * OPAL API definitions.
3 *
4 * Copyright 2011-2015 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef __OPAL_API_H
13#define __OPAL_API_H
14
15/****** OPAL APIs ******/
16
17/* Return codes */
18#define OPAL_SUCCESS 0
19#define OPAL_PARAMETER -1
20#define OPAL_BUSY -2
21#define OPAL_PARTIAL -3
22#define OPAL_CONSTRAINED -4
23#define OPAL_CLOSED -5
24#define OPAL_HARDWARE -6
25#define OPAL_UNSUPPORTED -7
26#define OPAL_PERMISSION -8
27#define OPAL_NO_MEM -9
28#define OPAL_RESOURCE -10
29#define OPAL_INTERNAL_ERROR -11
30#define OPAL_BUSY_EVENT -12
31#define OPAL_HARDWARE_FROZEN -13
32#define OPAL_WRONG_STATE -14
33#define OPAL_ASYNC_COMPLETION -15
34#define OPAL_EMPTY -16
35#define OPAL_I2C_TIMEOUT -17
36#define OPAL_I2C_INVALID_CMD -18
37#define OPAL_I2C_LBUS_PARITY -19
38#define OPAL_I2C_BKEND_OVERRUN -20
39#define OPAL_I2C_BKEND_ACCESS -21
40#define OPAL_I2C_ARBT_LOST -22
41#define OPAL_I2C_NACK_RCVD -23
42#define OPAL_I2C_STOP_ERR -24
43
44/* API Tokens (in r0) */
45#define OPAL_INVALID_CALL -1
46#define OPAL_TEST 0
47#define OPAL_CONSOLE_WRITE 1
48#define OPAL_CONSOLE_READ 2
49#define OPAL_RTC_READ 3
50#define OPAL_RTC_WRITE 4
51#define OPAL_CEC_POWER_DOWN 5
52#define OPAL_CEC_REBOOT 6
53#define OPAL_READ_NVRAM 7
54#define OPAL_WRITE_NVRAM 8
55#define OPAL_HANDLE_INTERRUPT 9
56#define OPAL_POLL_EVENTS 10
57#define OPAL_PCI_SET_HUB_TCE_MEMORY 11
58#define OPAL_PCI_SET_PHB_TCE_MEMORY 12
59#define OPAL_PCI_CONFIG_READ_BYTE 13
60#define OPAL_PCI_CONFIG_READ_HALF_WORD 14
61#define OPAL_PCI_CONFIG_READ_WORD 15
62#define OPAL_PCI_CONFIG_WRITE_BYTE 16
63#define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
64#define OPAL_PCI_CONFIG_WRITE_WORD 18
65#define OPAL_SET_XIVE 19
66#define OPAL_GET_XIVE 20
67#define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
68#define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
69#define OPAL_PCI_EEH_FREEZE_STATUS 23
70#define OPAL_PCI_SHPC 24
71#define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
72#define OPAL_PCI_EEH_FREEZE_CLEAR 26
73#define OPAL_PCI_PHB_MMIO_ENABLE 27
74#define OPAL_PCI_SET_PHB_MEM_WINDOW 28
75#define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
76#define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
77#define OPAL_PCI_SET_PE 31
78#define OPAL_PCI_SET_PELTV 32
79#define OPAL_PCI_SET_MVE 33
80#define OPAL_PCI_SET_MVE_ENABLE 34
81#define OPAL_PCI_GET_XIVE_REISSUE 35
82#define OPAL_PCI_SET_XIVE_REISSUE 36
83#define OPAL_PCI_SET_XIVE_PE 37
84#define OPAL_GET_XIVE_SOURCE 38
85#define OPAL_GET_MSI_32 39
86#define OPAL_GET_MSI_64 40
87#define OPAL_START_CPU 41
88#define OPAL_QUERY_CPU_STATUS 42
89#define OPAL_WRITE_OPPANEL 43 /* unimplemented */
90#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
91#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
92#define OPAL_PCI_RESET 49
93#define OPAL_PCI_GET_HUB_DIAG_DATA 50
94#define OPAL_PCI_GET_PHB_DIAG_DATA 51
95#define OPAL_PCI_FENCE_PHB 52
96#define OPAL_PCI_REINIT 53
97#define OPAL_PCI_MASK_PE_ERROR 54
98#define OPAL_SET_SLOT_LED_STATUS 55
99#define OPAL_GET_EPOW_STATUS 56
100#define OPAL_SET_SYSTEM_ATTENTION_LED 57
101#define OPAL_RESERVED1 58
102#define OPAL_RESERVED2 59
103#define OPAL_PCI_NEXT_ERROR 60
104#define OPAL_PCI_EEH_FREEZE_STATUS2 61
105#define OPAL_PCI_POLL 62
106#define OPAL_PCI_MSI_EOI 63
107#define OPAL_PCI_GET_PHB_DIAG_DATA2 64
108#define OPAL_XSCOM_READ 65
109#define OPAL_XSCOM_WRITE 66
110#define OPAL_LPC_READ 67
111#define OPAL_LPC_WRITE 68
112#define OPAL_RETURN_CPU 69
113#define OPAL_REINIT_CPUS 70
114#define OPAL_ELOG_READ 71
115#define OPAL_ELOG_WRITE 72
116#define OPAL_ELOG_ACK 73
117#define OPAL_ELOG_RESEND 74
118#define OPAL_ELOG_SIZE 75
119#define OPAL_FLASH_VALIDATE 76
120#define OPAL_FLASH_MANAGE 77
121#define OPAL_FLASH_UPDATE 78
122#define OPAL_RESYNC_TIMEBASE 79
123#define OPAL_CHECK_TOKEN 80
124#define OPAL_DUMP_INIT 81
125#define OPAL_DUMP_INFO 82
126#define OPAL_DUMP_READ 83
127#define OPAL_DUMP_ACK 84
128#define OPAL_GET_MSG 85
129#define OPAL_CHECK_ASYNC_COMPLETION 86
130#define OPAL_SYNC_HOST_REBOOT 87
131#define OPAL_SENSOR_READ 88
132#define OPAL_GET_PARAM 89
133#define OPAL_SET_PARAM 90
134#define OPAL_DUMP_RESEND 91
135#define OPAL_ELOG_SEND 92 /* Deprecated */
136#define OPAL_PCI_SET_PHB_CAPI_MODE 93
137#define OPAL_DUMP_INFO2 94
138#define OPAL_WRITE_OPPANEL_ASYNC 95
139#define OPAL_PCI_ERR_INJECT 96
140#define OPAL_PCI_EEH_FREEZE_SET 97
141#define OPAL_HANDLE_HMI 98
142#define OPAL_CONFIG_CPU_IDLE_STATE 99
143#define OPAL_SLW_SET_REG 100
144#define OPAL_REGISTER_DUMP_REGION 101
145#define OPAL_UNREGISTER_DUMP_REGION 102
146#define OPAL_WRITE_TPO 103
147#define OPAL_READ_TPO 104
148#define OPAL_GET_DPO_STATUS 105
149#define OPAL_OLD_I2C_REQUEST 106 /* Deprecated */
150#define OPAL_IPMI_SEND 107
151#define OPAL_IPMI_RECV 108
152#define OPAL_I2C_REQUEST 109
153#define OPAL_FLASH_READ 110
154#define OPAL_FLASH_WRITE 111
155#define OPAL_FLASH_ERASE 112
156#define OPAL_LAST 112
157
158/* Device tree flags */
159
160/* Flags set in power-mgmt nodes in device tree if
161 * respective idle states are supported in the platform.
162 */
163#define OPAL_PM_NAP_ENABLED 0x00010000
164#define OPAL_PM_SLEEP_ENABLED 0x00020000
165#define OPAL_PM_WINKLE_ENABLED 0x00040000
166#define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000 /* with workaround */
167
168#ifndef __ASSEMBLY__
169
170/* Other enums */
171enum OpalFreezeState {
172 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
173 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
174 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
175 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
176 OPAL_EEH_STOPPED_RESET = 4,
177 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
178 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
179};
180
181enum OpalEehFreezeActionToken {
182 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
183 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
184 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
185
186 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
187 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2,
188 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3
189};
190
191enum OpalPciStatusToken {
192 OPAL_EEH_NO_ERROR = 0,
193 OPAL_EEH_IOC_ERROR = 1,
194 OPAL_EEH_PHB_ERROR = 2,
195 OPAL_EEH_PE_ERROR = 3,
196 OPAL_EEH_PE_MMIO_ERROR = 4,
197 OPAL_EEH_PE_DMA_ERROR = 5
198};
199
200enum OpalPciErrorSeverity {
201 OPAL_EEH_SEV_NO_ERROR = 0,
202 OPAL_EEH_SEV_IOC_DEAD = 1,
203 OPAL_EEH_SEV_PHB_DEAD = 2,
204 OPAL_EEH_SEV_PHB_FENCED = 3,
205 OPAL_EEH_SEV_PE_ER = 4,
206 OPAL_EEH_SEV_INF = 5
207};
208
209enum OpalErrinjectType {
210 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0,
211 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1,
212};
213
214enum OpalErrinjectFunc {
215 /* IOA bus specific errors */
216 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0,
217 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1,
218 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2,
219 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3,
220 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4,
221 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5,
222 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6,
223 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7,
224 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8,
225 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9,
226 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10,
227 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11,
228 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12,
229 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13,
230 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14,
231 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15,
232 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16,
233 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17,
234 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18,
235 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19,
236};
237
238enum OpalMmioWindowType {
239 OPAL_M32_WINDOW_TYPE = 1,
240 OPAL_M64_WINDOW_TYPE = 2,
241 OPAL_IO_WINDOW_TYPE = 3
242};
243
244enum OpalExceptionHandler {
245 OPAL_MACHINE_CHECK_HANDLER = 1,
246 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
247 OPAL_SOFTPATCH_HANDLER = 3
248};
249
250enum OpalPendingState {
251 OPAL_EVENT_OPAL_INTERNAL = 0x1,
252 OPAL_EVENT_NVRAM = 0x2,
253 OPAL_EVENT_RTC = 0x4,
254 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
255 OPAL_EVENT_CONSOLE_INPUT = 0x10,
256 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
257 OPAL_EVENT_ERROR_LOG = 0x40,
258 OPAL_EVENT_EPOW = 0x80,
259 OPAL_EVENT_LED_STATUS = 0x100,
260 OPAL_EVENT_PCI_ERROR = 0x200,
261 OPAL_EVENT_DUMP_AVAIL = 0x400,
262 OPAL_EVENT_MSG_PENDING = 0x800,
263};
264
265enum OpalThreadStatus {
266 OPAL_THREAD_INACTIVE = 0x0,
267 OPAL_THREAD_STARTED = 0x1,
268 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
269};
270
271enum OpalPciBusCompare {
272 OpalPciBusAny = 0, /* Any bus number match */
273 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
274 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
275 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
276 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
277 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
278 OpalPciBusAll = 7, /* Match bus number exactly */
279};
280
281enum OpalDeviceCompare {
282 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
283 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
284};
285
286enum OpalFuncCompare {
287 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
288 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
289};
290
291enum OpalPeAction {
292 OPAL_UNMAP_PE = 0,
293 OPAL_MAP_PE = 1
294};
295
296enum OpalPeltvAction {
297 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
298 OPAL_ADD_PE_TO_DOMAIN = 1
299};
300
301enum OpalMveEnableAction {
302 OPAL_DISABLE_MVE = 0,
303 OPAL_ENABLE_MVE = 1
304};
305
306enum OpalM64Action {
307 OPAL_DISABLE_M64 = 0,
308 OPAL_ENABLE_M64_SPLIT = 1,
309 OPAL_ENABLE_M64_NON_SPLIT = 2
310};
311
312enum OpalPciResetScope {
313 OPAL_RESET_PHB_COMPLETE = 1,
314 OPAL_RESET_PCI_LINK = 2,
315 OPAL_RESET_PHB_ERROR = 3,
316 OPAL_RESET_PCI_HOT = 4,
317 OPAL_RESET_PCI_FUNDAMENTAL = 5,
318 OPAL_RESET_PCI_IODA_TABLE = 6
319};
320
321enum OpalPciReinitScope {
322 /*
323 * Note: we chose values that do not overlap
324 * OpalPciResetScope as OPAL v2 used the same
325 * enum for both
326 */
327 OPAL_REINIT_PCI_DEV = 1000
328};
329
330enum OpalPciResetState {
331 OPAL_DEASSERT_RESET = 0,
332 OPAL_ASSERT_RESET = 1
333};
334
335/*
336 * Address cycle types for LPC accesses. These also correspond
337 * to the content of the first cell of the "reg" property for
338 * device nodes on the LPC bus
339 */
340enum OpalLPCAddressType {
341 OPAL_LPC_MEM = 0,
342 OPAL_LPC_IO = 1,
343 OPAL_LPC_FW = 2,
344};
345
346enum opal_msg_type {
347 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
348 * additional params function-specific
349 */
350 OPAL_MSG_MEM_ERR,
351 OPAL_MSG_EPOW,
352 OPAL_MSG_SHUTDOWN, /* params[0] = 1 reboot, 0 shutdown */
353 OPAL_MSG_HMI_EVT,
354 OPAL_MSG_DPO,
355 OPAL_MSG_TYPE_MAX,
356};
357
358struct opal_msg {
359 __be32 msg_type;
360 __be32 reserved;
361 __be64 params[8];
362};
363
364/* System parameter permission */
365enum OpalSysparamPerm {
366 OPAL_SYSPARAM_READ = 0x1,
367 OPAL_SYSPARAM_WRITE = 0x2,
368 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
369};
370
371enum {
372 OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
373};
374
375struct opal_ipmi_msg {
376 uint8_t version;
377 uint8_t netfn;
378 uint8_t cmd;
379 uint8_t data[];
380};
381
382/* FSP memory errors handling */
383enum OpalMemErr_Version {
384 OpalMemErr_V1 = 1,
385};
386
387enum OpalMemErrType {
388 OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
389 OPAL_MEM_ERR_TYPE_DYN_DALLOC,
390};
391
392/* Memory Reilience error type */
393enum OpalMemErr_ResilErrType {
394 OPAL_MEM_RESILIENCE_CE = 0,
395 OPAL_MEM_RESILIENCE_UE,
396 OPAL_MEM_RESILIENCE_UE_SCRUB,
397};
398
399/* Dynamic Memory Deallocation type */
400enum OpalMemErr_DynErrType {
401 OPAL_MEM_DYNAMIC_DEALLOC = 0,
402};
403
404struct OpalMemoryErrorData {
405 enum OpalMemErr_Version version:8; /* 0x00 */
406 enum OpalMemErrType type:8; /* 0x01 */
407 __be16 flags; /* 0x02 */
408 uint8_t reserved_1[4]; /* 0x04 */
409
410 union {
411 /* Memory Resilience corrected/uncorrected error info */
412 struct {
413 enum OpalMemErr_ResilErrType resil_err_type:8;
414 uint8_t reserved_1[7];
415 __be64 physical_address_start;
416 __be64 physical_address_end;
417 } resilience;
418 /* Dynamic memory deallocation error info */
419 struct {
420 enum OpalMemErr_DynErrType dyn_err_type:8;
421 uint8_t reserved_1[7];
422 __be64 physical_address_start;
423 __be64 physical_address_end;
424 } dyn_dealloc;
425 } u;
426};
427
428/* HMI interrupt event */
429enum OpalHMI_Version {
430 OpalHMIEvt_V1 = 1,
431};
432
433enum OpalHMI_Severity {
434 OpalHMI_SEV_NO_ERROR = 0,
435 OpalHMI_SEV_WARNING = 1,
436 OpalHMI_SEV_ERROR_SYNC = 2,
437 OpalHMI_SEV_FATAL = 3,
438};
439
440enum OpalHMI_Disposition {
441 OpalHMI_DISPOSITION_RECOVERED = 0,
442 OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
443};
444
445enum OpalHMI_ErrType {
446 OpalHMI_ERROR_MALFUNC_ALERT = 0,
447 OpalHMI_ERROR_PROC_RECOV_DONE,
448 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
449 OpalHMI_ERROR_PROC_RECOV_MASKED,
450 OpalHMI_ERROR_TFAC,
451 OpalHMI_ERROR_TFMR_PARITY,
452 OpalHMI_ERROR_HA_OVERFLOW_WARN,
453 OpalHMI_ERROR_XSCOM_FAIL,
454 OpalHMI_ERROR_XSCOM_DONE,
455 OpalHMI_ERROR_SCOM_FIR,
456 OpalHMI_ERROR_DEBUG_TRIG_FIR,
457 OpalHMI_ERROR_HYP_RESOURCE,
458 OpalHMI_ERROR_CAPP_RECOVERY,
459};
460
461struct OpalHMIEvent {
462 uint8_t version; /* 0x00 */
463 uint8_t severity; /* 0x01 */
464 uint8_t type; /* 0x02 */
465 uint8_t disposition; /* 0x03 */
466 uint8_t reserved_1[4]; /* 0x04 */
467
468 __be64 hmer;
469 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
470 __be64 tfmr;
471};
472
473enum {
474 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
475 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
476 OPAL_P7IOC_DIAG_TYPE_BI = 2,
477 OPAL_P7IOC_DIAG_TYPE_CI = 3,
478 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
479 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
480 OPAL_P7IOC_DIAG_TYPE_LAST = 6
481};
482
483struct OpalIoP7IOCErrorData {
484 __be16 type;
485
486 /* GEM */
487 __be64 gemXfir;
488 __be64 gemRfir;
489 __be64 gemRirqfir;
490 __be64 gemMask;
491 __be64 gemRwof;
492
493 /* LEM */
494 __be64 lemFir;
495 __be64 lemErrMask;
496 __be64 lemAction0;
497 __be64 lemAction1;
498 __be64 lemWof;
499
500 union {
501 struct OpalIoP7IOCRgcErrorData {
502 __be64 rgcStatus; /* 3E1C10 */
503 __be64 rgcLdcp; /* 3E1C18 */
504 }rgc;
505 struct OpalIoP7IOCBiErrorData {
506 __be64 biLdcp0; /* 3C0100, 3C0118 */
507 __be64 biLdcp1; /* 3C0108, 3C0120 */
508 __be64 biLdcp2; /* 3C0110, 3C0128 */
509 __be64 biFenceStatus; /* 3C0130, 3C0130 */
510
511 uint8_t biDownbound; /* BI Downbound or Upbound */
512 }bi;
513 struct OpalIoP7IOCCiErrorData {
514 __be64 ciPortStatus; /* 3Dn008 */
515 __be64 ciPortLdcp; /* 3Dn010 */
516
517 uint8_t ciPort; /* Index of CI port: 0/1 */
518 }ci;
519 };
520};
521
522/**
523 * This structure defines the overlay which will be used to store PHB error
524 * data upon request.
525 */
526enum {
527 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
528};
529
530enum {
531 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
532 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
533};
534
535enum {
536 OPAL_P7IOC_NUM_PEST_REGS = 128,
537 OPAL_PHB3_NUM_PEST_REGS = 256
538};
539
540struct OpalIoPhbErrorCommon {
541 __be32 version;
542 __be32 ioType;
543 __be32 len;
544};
545
546struct OpalIoP7IOCPhbErrorData {
547 struct OpalIoPhbErrorCommon common;
548
549 __be32 brdgCtl;
550
551 // P7IOC utl regs
552 __be32 portStatusReg;
553 __be32 rootCmplxStatus;
554 __be32 busAgentStatus;
555
556 // P7IOC cfg regs
557 __be32 deviceStatus;
558 __be32 slotStatus;
559 __be32 linkStatus;
560 __be32 devCmdStatus;
561 __be32 devSecStatus;
562
563 // cfg AER regs
564 __be32 rootErrorStatus;
565 __be32 uncorrErrorStatus;
566 __be32 corrErrorStatus;
567 __be32 tlpHdr1;
568 __be32 tlpHdr2;
569 __be32 tlpHdr3;
570 __be32 tlpHdr4;
571 __be32 sourceId;
572
573 __be32 rsv3;
574
575 // Record data about the call to allocate a buffer.
576 __be64 errorClass;
577 __be64 correlator;
578
579 //P7IOC MMIO Error Regs
580 __be64 p7iocPlssr; // n120
581 __be64 p7iocCsr; // n110
582 __be64 lemFir; // nC00
583 __be64 lemErrorMask; // nC18
584 __be64 lemWOF; // nC40
585 __be64 phbErrorStatus; // nC80
586 __be64 phbFirstErrorStatus; // nC88
587 __be64 phbErrorLog0; // nCC0
588 __be64 phbErrorLog1; // nCC8
589 __be64 mmioErrorStatus; // nD00
590 __be64 mmioFirstErrorStatus; // nD08
591 __be64 mmioErrorLog0; // nD40
592 __be64 mmioErrorLog1; // nD48
593 __be64 dma0ErrorStatus; // nD80
594 __be64 dma0FirstErrorStatus; // nD88
595 __be64 dma0ErrorLog0; // nDC0
596 __be64 dma0ErrorLog1; // nDC8
597 __be64 dma1ErrorStatus; // nE00
598 __be64 dma1FirstErrorStatus; // nE08
599 __be64 dma1ErrorLog0; // nE40
600 __be64 dma1ErrorLog1; // nE48
601 __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
602 __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
603};
604
605struct OpalIoPhb3ErrorData {
606 struct OpalIoPhbErrorCommon common;
607
608 __be32 brdgCtl;
609
610 /* PHB3 UTL regs */
611 __be32 portStatusReg;
612 __be32 rootCmplxStatus;
613 __be32 busAgentStatus;
614
615 /* PHB3 cfg regs */
616 __be32 deviceStatus;
617 __be32 slotStatus;
618 __be32 linkStatus;
619 __be32 devCmdStatus;
620 __be32 devSecStatus;
621
622 /* cfg AER regs */
623 __be32 rootErrorStatus;
624 __be32 uncorrErrorStatus;
625 __be32 corrErrorStatus;
626 __be32 tlpHdr1;
627 __be32 tlpHdr2;
628 __be32 tlpHdr3;
629 __be32 tlpHdr4;
630 __be32 sourceId;
631
632 __be32 rsv3;
633
634 /* Record data about the call to allocate a buffer */
635 __be64 errorClass;
636 __be64 correlator;
637
638 /* PHB3 MMIO Error Regs */
639 __be64 nFir; /* 000 */
640 __be64 nFirMask; /* 003 */
641 __be64 nFirWOF; /* 008 */
642 __be64 phbPlssr; /* 120 */
643 __be64 phbCsr; /* 110 */
644 __be64 lemFir; /* C00 */
645 __be64 lemErrorMask; /* C18 */
646 __be64 lemWOF; /* C40 */
647 __be64 phbErrorStatus; /* C80 */
648 __be64 phbFirstErrorStatus; /* C88 */
649 __be64 phbErrorLog0; /* CC0 */
650 __be64 phbErrorLog1; /* CC8 */
651 __be64 mmioErrorStatus; /* D00 */
652 __be64 mmioFirstErrorStatus; /* D08 */
653 __be64 mmioErrorLog0; /* D40 */
654 __be64 mmioErrorLog1; /* D48 */
655 __be64 dma0ErrorStatus; /* D80 */
656 __be64 dma0FirstErrorStatus; /* D88 */
657 __be64 dma0ErrorLog0; /* DC0 */
658 __be64 dma0ErrorLog1; /* DC8 */
659 __be64 dma1ErrorStatus; /* E00 */
660 __be64 dma1FirstErrorStatus; /* E08 */
661 __be64 dma1ErrorLog0; /* E40 */
662 __be64 dma1ErrorLog1; /* E48 */
663 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
664 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
665};
666
667enum {
668 OPAL_REINIT_CPUS_HILE_BE = (1 << 0),
669 OPAL_REINIT_CPUS_HILE_LE = (1 << 1),
670};
671
672typedef struct oppanel_line {
673 __be64 line;
674 __be64 line_len;
675} oppanel_line_t;
676
677/*
678 * SG entries
679 *
680 * WARNING: The current implementation requires each entry
681 * to represent a block that is 4k aligned *and* each block
682 * size except the last one in the list to be as well.
683 */
684struct opal_sg_entry {
685 __be64 data;
686 __be64 length;
687};
688
689/*
690 * Candiate image SG list.
691 *
692 * length = VER | length
693 */
694struct opal_sg_list {
695 __be64 length;
696 __be64 next;
697 struct opal_sg_entry entry[];
698};
699
700/*
701 * Dump region ID range usable by the OS
702 */
703#define OPAL_DUMP_REGION_HOST_START 0x80
704#define OPAL_DUMP_REGION_LOG_BUF 0x80
705#define OPAL_DUMP_REGION_HOST_END 0xFF
706
707/* CAPI modes for PHB */
708enum {
709 OPAL_PHB_CAPI_MODE_PCIE = 0,
710 OPAL_PHB_CAPI_MODE_CAPI = 1,
711 OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2,
712 OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
713};
714
715/* OPAL I2C request */
716struct opal_i2c_request {
717 uint8_t type;
718#define OPAL_I2C_RAW_READ 0
719#define OPAL_I2C_RAW_WRITE 1
720#define OPAL_I2C_SM_READ 2
721#define OPAL_I2C_SM_WRITE 3
722 uint8_t flags;
723#define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */
724 uint8_t subaddr_sz; /* Max 4 */
725 uint8_t reserved;
726 __be16 addr; /* 7 or 10 bit address */
727 __be16 reserved2;
728 __be32 subaddr; /* Sub-address if any */
729 __be32 size; /* Data size */
730 __be64 buffer_ra; /* Buffer real address */
731};
732
733#endif /* __ASSEMBLY__ */
734
735#endif /* __OPAL_API_H */
diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 9ee0a30a02ce..042af1abfc4d 100644
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -9,755 +9,17 @@
9 * 2 of the License, or (at your option) any later version. 9 * 2 of the License, or (at your option) any later version.
10 */ 10 */
11 11
12#ifndef __OPAL_H 12#ifndef _ASM_POWERPC_OPAL_H
13#define __OPAL_H 13#define _ASM_POWERPC_OPAL_H
14 14
15#ifndef __ASSEMBLY__ 15#include <asm/opal-api.h>
16/*
17 * SG entry
18 *
19 * WARNING: The current implementation requires each entry
20 * to represent a block that is 4k aligned *and* each block
21 * size except the last one in the list to be as well.
22 */
23struct opal_sg_entry {
24 __be64 data;
25 __be64 length;
26};
27
28/* SG list */
29struct opal_sg_list {
30 __be64 length;
31 __be64 next;
32 struct opal_sg_entry entry[];
33};
34
35/* We calculate number of sg entries based on PAGE_SIZE */
36#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
37
38#endif /* __ASSEMBLY__ */
39
40/****** OPAL APIs ******/
41
42/* Return codes */
43#define OPAL_SUCCESS 0
44#define OPAL_PARAMETER -1
45#define OPAL_BUSY -2
46#define OPAL_PARTIAL -3
47#define OPAL_CONSTRAINED -4
48#define OPAL_CLOSED -5
49#define OPAL_HARDWARE -6
50#define OPAL_UNSUPPORTED -7
51#define OPAL_PERMISSION -8
52#define OPAL_NO_MEM -9
53#define OPAL_RESOURCE -10
54#define OPAL_INTERNAL_ERROR -11
55#define OPAL_BUSY_EVENT -12
56#define OPAL_HARDWARE_FROZEN -13
57#define OPAL_WRONG_STATE -14
58#define OPAL_ASYNC_COMPLETION -15
59#define OPAL_I2C_TIMEOUT -17
60#define OPAL_I2C_INVALID_CMD -18
61#define OPAL_I2C_LBUS_PARITY -19
62#define OPAL_I2C_BKEND_OVERRUN -20
63#define OPAL_I2C_BKEND_ACCESS -21
64#define OPAL_I2C_ARBT_LOST -22
65#define OPAL_I2C_NACK_RCVD -23
66#define OPAL_I2C_STOP_ERR -24
67
68/* API Tokens (in r0) */
69#define OPAL_INVALID_CALL -1
70#define OPAL_CONSOLE_WRITE 1
71#define OPAL_CONSOLE_READ 2
72#define OPAL_RTC_READ 3
73#define OPAL_RTC_WRITE 4
74#define OPAL_CEC_POWER_DOWN 5
75#define OPAL_CEC_REBOOT 6
76#define OPAL_READ_NVRAM 7
77#define OPAL_WRITE_NVRAM 8
78#define OPAL_HANDLE_INTERRUPT 9
79#define OPAL_POLL_EVENTS 10
80#define OPAL_PCI_SET_HUB_TCE_MEMORY 11
81#define OPAL_PCI_SET_PHB_TCE_MEMORY 12
82#define OPAL_PCI_CONFIG_READ_BYTE 13
83#define OPAL_PCI_CONFIG_READ_HALF_WORD 14
84#define OPAL_PCI_CONFIG_READ_WORD 15
85#define OPAL_PCI_CONFIG_WRITE_BYTE 16
86#define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
87#define OPAL_PCI_CONFIG_WRITE_WORD 18
88#define OPAL_SET_XIVE 19
89#define OPAL_GET_XIVE 20
90#define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
91#define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
92#define OPAL_PCI_EEH_FREEZE_STATUS 23
93#define OPAL_PCI_SHPC 24
94#define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
95#define OPAL_PCI_EEH_FREEZE_CLEAR 26
96#define OPAL_PCI_PHB_MMIO_ENABLE 27
97#define OPAL_PCI_SET_PHB_MEM_WINDOW 28
98#define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
99#define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
100#define OPAL_PCI_SET_PE 31
101#define OPAL_PCI_SET_PELTV 32
102#define OPAL_PCI_SET_MVE 33
103#define OPAL_PCI_SET_MVE_ENABLE 34
104#define OPAL_PCI_GET_XIVE_REISSUE 35
105#define OPAL_PCI_SET_XIVE_REISSUE 36
106#define OPAL_PCI_SET_XIVE_PE 37
107#define OPAL_GET_XIVE_SOURCE 38
108#define OPAL_GET_MSI_32 39
109#define OPAL_GET_MSI_64 40
110#define OPAL_START_CPU 41
111#define OPAL_QUERY_CPU_STATUS 42
112#define OPAL_WRITE_OPPANEL 43
113#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
114#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
115#define OPAL_PCI_RESET 49
116#define OPAL_PCI_GET_HUB_DIAG_DATA 50
117#define OPAL_PCI_GET_PHB_DIAG_DATA 51
118#define OPAL_PCI_FENCE_PHB 52
119#define OPAL_PCI_REINIT 53
120#define OPAL_PCI_MASK_PE_ERROR 54
121#define OPAL_SET_SLOT_LED_STATUS 55
122#define OPAL_GET_EPOW_STATUS 56
123#define OPAL_SET_SYSTEM_ATTENTION_LED 57
124#define OPAL_RESERVED1 58
125#define OPAL_RESERVED2 59
126#define OPAL_PCI_NEXT_ERROR 60
127#define OPAL_PCI_EEH_FREEZE_STATUS2 61
128#define OPAL_PCI_POLL 62
129#define OPAL_PCI_MSI_EOI 63
130#define OPAL_PCI_GET_PHB_DIAG_DATA2 64
131#define OPAL_XSCOM_READ 65
132#define OPAL_XSCOM_WRITE 66
133#define OPAL_LPC_READ 67
134#define OPAL_LPC_WRITE 68
135#define OPAL_RETURN_CPU 69
136#define OPAL_REINIT_CPUS 70
137#define OPAL_ELOG_READ 71
138#define OPAL_ELOG_WRITE 72
139#define OPAL_ELOG_ACK 73
140#define OPAL_ELOG_RESEND 74
141#define OPAL_ELOG_SIZE 75
142#define OPAL_FLASH_VALIDATE 76
143#define OPAL_FLASH_MANAGE 77
144#define OPAL_FLASH_UPDATE 78
145#define OPAL_RESYNC_TIMEBASE 79
146#define OPAL_CHECK_TOKEN 80
147#define OPAL_DUMP_INIT 81
148#define OPAL_DUMP_INFO 82
149#define OPAL_DUMP_READ 83
150#define OPAL_DUMP_ACK 84
151#define OPAL_GET_MSG 85
152#define OPAL_CHECK_ASYNC_COMPLETION 86
153#define OPAL_SYNC_HOST_REBOOT 87
154#define OPAL_SENSOR_READ 88
155#define OPAL_GET_PARAM 89
156#define OPAL_SET_PARAM 90
157#define OPAL_DUMP_RESEND 91
158#define OPAL_PCI_SET_PHB_CXL_MODE 93
159#define OPAL_DUMP_INFO2 94
160#define OPAL_PCI_ERR_INJECT 96
161#define OPAL_PCI_EEH_FREEZE_SET 97
162#define OPAL_HANDLE_HMI 98
163#define OPAL_CONFIG_CPU_IDLE_STATE 99
164#define OPAL_SLW_SET_REG 100
165#define OPAL_REGISTER_DUMP_REGION 101
166#define OPAL_UNREGISTER_DUMP_REGION 102
167#define OPAL_WRITE_TPO 103
168#define OPAL_READ_TPO 104
169#define OPAL_IPMI_SEND 107
170#define OPAL_IPMI_RECV 108
171#define OPAL_I2C_REQUEST 109
172
173/* Device tree flags */
174
175/* Flags set in power-mgmt nodes in device tree if
176 * respective idle states are supported in the platform.
177 */
178#define OPAL_PM_NAP_ENABLED 0x00010000
179#define OPAL_PM_SLEEP_ENABLED 0x00020000
180#define OPAL_PM_WINKLE_ENABLED 0x00040000
181#define OPAL_PM_SLEEP_ENABLED_ER1 0x00080000
182 16
183#ifndef __ASSEMBLY__ 17#ifndef __ASSEMBLY__
184 18
185#include <linux/notifier.h> 19#include <linux/notifier.h>
186 20
187/* Other enums */ 21/* We calculate number of sg entries based on PAGE_SIZE */
188enum OpalVendorApiTokens { 22#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
189 OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
190};
191
192enum OpalFreezeState {
193 OPAL_EEH_STOPPED_NOT_FROZEN = 0,
194 OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
195 OPAL_EEH_STOPPED_DMA_FREEZE = 2,
196 OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
197 OPAL_EEH_STOPPED_RESET = 4,
198 OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
199 OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
200};
201
202enum OpalEehFreezeActionToken {
203 OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
204 OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
205 OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3,
206
207 OPAL_EEH_ACTION_SET_FREEZE_MMIO = 1,
208 OPAL_EEH_ACTION_SET_FREEZE_DMA = 2,
209 OPAL_EEH_ACTION_SET_FREEZE_ALL = 3
210};
211
212enum OpalPciStatusToken {
213 OPAL_EEH_NO_ERROR = 0,
214 OPAL_EEH_IOC_ERROR = 1,
215 OPAL_EEH_PHB_ERROR = 2,
216 OPAL_EEH_PE_ERROR = 3,
217 OPAL_EEH_PE_MMIO_ERROR = 4,
218 OPAL_EEH_PE_DMA_ERROR = 5
219};
220
221enum OpalPciErrorSeverity {
222 OPAL_EEH_SEV_NO_ERROR = 0,
223 OPAL_EEH_SEV_IOC_DEAD = 1,
224 OPAL_EEH_SEV_PHB_DEAD = 2,
225 OPAL_EEH_SEV_PHB_FENCED = 3,
226 OPAL_EEH_SEV_PE_ER = 4,
227 OPAL_EEH_SEV_INF = 5
228};
229
230enum OpalErrinjectType {
231 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR = 0,
232 OPAL_ERR_INJECT_TYPE_IOA_BUS_ERR64 = 1,
233};
234
235enum OpalErrinjectFunc {
236 /* IOA bus specific errors */
237 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_ADDR = 0,
238 OPAL_ERR_INJECT_FUNC_IOA_LD_MEM_DATA = 1,
239 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_ADDR = 2,
240 OPAL_ERR_INJECT_FUNC_IOA_LD_IO_DATA = 3,
241 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_ADDR = 4,
242 OPAL_ERR_INJECT_FUNC_IOA_LD_CFG_DATA = 5,
243 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_ADDR = 6,
244 OPAL_ERR_INJECT_FUNC_IOA_ST_MEM_DATA = 7,
245 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_ADDR = 8,
246 OPAL_ERR_INJECT_FUNC_IOA_ST_IO_DATA = 9,
247 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_ADDR = 10,
248 OPAL_ERR_INJECT_FUNC_IOA_ST_CFG_DATA = 11,
249 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_ADDR = 12,
250 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_DATA = 13,
251 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_MASTER = 14,
252 OPAL_ERR_INJECT_FUNC_IOA_DMA_RD_TARGET = 15,
253 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_ADDR = 16,
254 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_DATA = 17,
255 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_MASTER = 18,
256 OPAL_ERR_INJECT_FUNC_IOA_DMA_WR_TARGET = 19,
257};
258
259enum OpalShpcAction {
260 OPAL_SHPC_GET_LINK_STATE = 0,
261 OPAL_SHPC_GET_SLOT_STATE = 1
262};
263
264enum OpalShpcLinkState {
265 OPAL_SHPC_LINK_DOWN = 0,
266 OPAL_SHPC_LINK_UP = 1
267};
268
269enum OpalMmioWindowType {
270 OPAL_M32_WINDOW_TYPE = 1,
271 OPAL_M64_WINDOW_TYPE = 2,
272 OPAL_IO_WINDOW_TYPE = 3
273};
274
275enum OpalShpcSlotState {
276 OPAL_SHPC_DEV_NOT_PRESENT = 0,
277 OPAL_SHPC_DEV_PRESENT = 1
278};
279
280enum OpalExceptionHandler {
281 OPAL_MACHINE_CHECK_HANDLER = 1,
282 OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
283 OPAL_SOFTPATCH_HANDLER = 3
284};
285
286enum OpalPendingState {
287 OPAL_EVENT_OPAL_INTERNAL = 0x1,
288 OPAL_EVENT_NVRAM = 0x2,
289 OPAL_EVENT_RTC = 0x4,
290 OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
291 OPAL_EVENT_CONSOLE_INPUT = 0x10,
292 OPAL_EVENT_ERROR_LOG_AVAIL = 0x20,
293 OPAL_EVENT_ERROR_LOG = 0x40,
294 OPAL_EVENT_EPOW = 0x80,
295 OPAL_EVENT_LED_STATUS = 0x100,
296 OPAL_EVENT_PCI_ERROR = 0x200,
297 OPAL_EVENT_DUMP_AVAIL = 0x400,
298 OPAL_EVENT_MSG_PENDING = 0x800,
299};
300
301enum OpalMessageType {
302 OPAL_MSG_ASYNC_COMP = 0, /* params[0] = token, params[1] = rc,
303 * additional params function-specific
304 */
305 OPAL_MSG_MEM_ERR,
306 OPAL_MSG_EPOW,
307 OPAL_MSG_SHUTDOWN, /* params[0] = 1 reboot, 0 shutdown */
308 OPAL_MSG_HMI_EVT,
309 OPAL_MSG_TYPE_MAX,
310};
311
312enum OpalThreadStatus {
313 OPAL_THREAD_INACTIVE = 0x0,
314 OPAL_THREAD_STARTED = 0x1,
315 OPAL_THREAD_UNAVAILABLE = 0x2 /* opal-v3 */
316};
317
318enum OpalPciBusCompare {
319 OpalPciBusAny = 0, /* Any bus number match */
320 OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
321 OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
322 OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
323 OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
324 OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
325 OpalPciBusAll = 7, /* Match bus number exactly */
326};
327
328enum OpalDeviceCompare {
329 OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
330 OPAL_COMPARE_RID_DEVICE_NUMBER = 1
331};
332
333enum OpalFuncCompare {
334 OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
335 OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
336};
337
338enum OpalPeAction {
339 OPAL_UNMAP_PE = 0,
340 OPAL_MAP_PE = 1
341};
342
343enum OpalPeltvAction {
344 OPAL_REMOVE_PE_FROM_DOMAIN = 0,
345 OPAL_ADD_PE_TO_DOMAIN = 1
346};
347
348enum OpalMveEnableAction {
349 OPAL_DISABLE_MVE = 0,
350 OPAL_ENABLE_MVE = 1
351};
352
353enum OpalM64EnableAction {
354 OPAL_DISABLE_M64 = 0,
355 OPAL_ENABLE_M64_SPLIT = 1,
356 OPAL_ENABLE_M64_NON_SPLIT = 2
357};
358
359enum OpalPciResetScope {
360 OPAL_RESET_PHB_COMPLETE = 1,
361 OPAL_RESET_PCI_LINK = 2,
362 OPAL_RESET_PHB_ERROR = 3,
363 OPAL_RESET_PCI_HOT = 4,
364 OPAL_RESET_PCI_FUNDAMENTAL = 5,
365 OPAL_RESET_PCI_IODA_TABLE = 6
366};
367
368enum OpalPciReinitScope {
369 OPAL_REINIT_PCI_DEV = 1000
370};
371
372enum OpalPciResetState {
373 OPAL_DEASSERT_RESET = 0,
374 OPAL_ASSERT_RESET = 1
375};
376
377enum OpalPciMaskAction {
378 OPAL_UNMASK_ERROR_TYPE = 0,
379 OPAL_MASK_ERROR_TYPE = 1
380};
381
382enum OpalSlotLedType {
383 OPAL_SLOT_LED_ID_TYPE = 0,
384 OPAL_SLOT_LED_FAULT_TYPE = 1
385};
386
387enum OpalLedAction {
388 OPAL_TURN_OFF_LED = 0,
389 OPAL_TURN_ON_LED = 1,
390 OPAL_QUERY_LED_STATE_AFTER_BUSY = 2
391};
392
393enum OpalEpowStatus {
394 OPAL_EPOW_NONE = 0,
395 OPAL_EPOW_UPS = 1,
396 OPAL_EPOW_OVER_AMBIENT_TEMP = 2,
397 OPAL_EPOW_OVER_INTERNAL_TEMP = 3
398};
399
400/*
401 * Address cycle types for LPC accesses. These also correspond
402 * to the content of the first cell of the "reg" property for
403 * device nodes on the LPC bus
404 */
405enum OpalLPCAddressType {
406 OPAL_LPC_MEM = 0,
407 OPAL_LPC_IO = 1,
408 OPAL_LPC_FW = 2,
409};
410
411/* System parameter permission */
412enum OpalSysparamPerm {
413 OPAL_SYSPARAM_READ = 0x1,
414 OPAL_SYSPARAM_WRITE = 0x2,
415 OPAL_SYSPARAM_RW = (OPAL_SYSPARAM_READ | OPAL_SYSPARAM_WRITE),
416};
417
418struct opal_msg {
419 __be32 msg_type;
420 __be32 reserved;
421 __be64 params[8];
422};
423
424enum {
425 OPAL_IPMI_MSG_FORMAT_VERSION_1 = 1,
426};
427
428struct opal_ipmi_msg {
429 uint8_t version;
430 uint8_t netfn;
431 uint8_t cmd;
432 uint8_t data[];
433};
434
435/* FSP memory errors handling */
436enum OpalMemErr_Version {
437 OpalMemErr_V1 = 1,
438};
439
440enum OpalMemErrType {
441 OPAL_MEM_ERR_TYPE_RESILIENCE = 0,
442 OPAL_MEM_ERR_TYPE_DYN_DALLOC,
443 OPAL_MEM_ERR_TYPE_SCRUB,
444};
445
446/* Memory Reilience error type */
447enum OpalMemErr_ResilErrType {
448 OPAL_MEM_RESILIENCE_CE = 0,
449 OPAL_MEM_RESILIENCE_UE,
450 OPAL_MEM_RESILIENCE_UE_SCRUB,
451};
452
453/* Dynamic Memory Deallocation type */
454enum OpalMemErr_DynErrType {
455 OPAL_MEM_DYNAMIC_DEALLOC = 0,
456};
457
458/* OpalMemoryErrorData->flags */
459#define OPAL_MEM_CORRECTED_ERROR 0x0001
460#define OPAL_MEM_THRESHOLD_EXCEEDED 0x0002
461#define OPAL_MEM_ACK_REQUIRED 0x8000
462
463struct OpalMemoryErrorData {
464 enum OpalMemErr_Version version:8; /* 0x00 */
465 enum OpalMemErrType type:8; /* 0x01 */
466 __be16 flags; /* 0x02 */
467 uint8_t reserved_1[4]; /* 0x04 */
468
469 union {
470 /* Memory Resilience corrected/uncorrected error info */
471 struct {
472 enum OpalMemErr_ResilErrType resil_err_type:8;
473 uint8_t reserved_1[7];
474 __be64 physical_address_start;
475 __be64 physical_address_end;
476 } resilience;
477 /* Dynamic memory deallocation error info */
478 struct {
479 enum OpalMemErr_DynErrType dyn_err_type:8;
480 uint8_t reserved_1[7];
481 __be64 physical_address_start;
482 __be64 physical_address_end;
483 } dyn_dealloc;
484 } u;
485};
486
487/* HMI interrupt event */
488enum OpalHMI_Version {
489 OpalHMIEvt_V1 = 1,
490};
491
492enum OpalHMI_Severity {
493 OpalHMI_SEV_NO_ERROR = 0,
494 OpalHMI_SEV_WARNING = 1,
495 OpalHMI_SEV_ERROR_SYNC = 2,
496 OpalHMI_SEV_FATAL = 3,
497};
498
499enum OpalHMI_Disposition {
500 OpalHMI_DISPOSITION_RECOVERED = 0,
501 OpalHMI_DISPOSITION_NOT_RECOVERED = 1,
502};
503
504enum OpalHMI_ErrType {
505 OpalHMI_ERROR_MALFUNC_ALERT = 0,
506 OpalHMI_ERROR_PROC_RECOV_DONE,
507 OpalHMI_ERROR_PROC_RECOV_DONE_AGAIN,
508 OpalHMI_ERROR_PROC_RECOV_MASKED,
509 OpalHMI_ERROR_TFAC,
510 OpalHMI_ERROR_TFMR_PARITY,
511 OpalHMI_ERROR_HA_OVERFLOW_WARN,
512 OpalHMI_ERROR_XSCOM_FAIL,
513 OpalHMI_ERROR_XSCOM_DONE,
514 OpalHMI_ERROR_SCOM_FIR,
515 OpalHMI_ERROR_DEBUG_TRIG_FIR,
516 OpalHMI_ERROR_HYP_RESOURCE,
517};
518
519struct OpalHMIEvent {
520 uint8_t version; /* 0x00 */
521 uint8_t severity; /* 0x01 */
522 uint8_t type; /* 0x02 */
523 uint8_t disposition; /* 0x03 */
524 uint8_t reserved_1[4]; /* 0x04 */
525
526 __be64 hmer;
527 /* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
528 __be64 tfmr;
529};
530
531enum {
532 OPAL_P7IOC_DIAG_TYPE_NONE = 0,
533 OPAL_P7IOC_DIAG_TYPE_RGC = 1,
534 OPAL_P7IOC_DIAG_TYPE_BI = 2,
535 OPAL_P7IOC_DIAG_TYPE_CI = 3,
536 OPAL_P7IOC_DIAG_TYPE_MISC = 4,
537 OPAL_P7IOC_DIAG_TYPE_I2C = 5,
538 OPAL_P7IOC_DIAG_TYPE_LAST = 6
539};
540
541struct OpalIoP7IOCErrorData {
542 __be16 type;
543
544 /* GEM */
545 __be64 gemXfir;
546 __be64 gemRfir;
547 __be64 gemRirqfir;
548 __be64 gemMask;
549 __be64 gemRwof;
550
551 /* LEM */
552 __be64 lemFir;
553 __be64 lemErrMask;
554 __be64 lemAction0;
555 __be64 lemAction1;
556 __be64 lemWof;
557
558 union {
559 struct OpalIoP7IOCRgcErrorData {
560 __be64 rgcStatus; /* 3E1C10 */
561 __be64 rgcLdcp; /* 3E1C18 */
562 }rgc;
563 struct OpalIoP7IOCBiErrorData {
564 __be64 biLdcp0; /* 3C0100, 3C0118 */
565 __be64 biLdcp1; /* 3C0108, 3C0120 */
566 __be64 biLdcp2; /* 3C0110, 3C0128 */
567 __be64 biFenceStatus; /* 3C0130, 3C0130 */
568
569 u8 biDownbound; /* BI Downbound or Upbound */
570 }bi;
571 struct OpalIoP7IOCCiErrorData {
572 __be64 ciPortStatus; /* 3Dn008 */
573 __be64 ciPortLdcp; /* 3Dn010 */
574
575 u8 ciPort; /* Index of CI port: 0/1 */
576 }ci;
577 };
578};
579
580/**
581 * This structure defines the overlay which will be used to store PHB error
582 * data upon request.
583 */
584enum {
585 OPAL_PHB_ERROR_DATA_VERSION_1 = 1,
586};
587
588enum {
589 OPAL_PHB_ERROR_DATA_TYPE_P7IOC = 1,
590 OPAL_PHB_ERROR_DATA_TYPE_PHB3 = 2
591};
592
593enum {
594 OPAL_P7IOC_NUM_PEST_REGS = 128,
595 OPAL_PHB3_NUM_PEST_REGS = 256
596};
597
598/* CAPI modes for PHB */
599enum {
600 OPAL_PHB_CAPI_MODE_PCIE = 0,
601 OPAL_PHB_CAPI_MODE_CAPI = 1,
602 OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2,
603 OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
604};
605
606struct OpalIoPhbErrorCommon {
607 __be32 version;
608 __be32 ioType;
609 __be32 len;
610};
611
612struct OpalIoP7IOCPhbErrorData {
613 struct OpalIoPhbErrorCommon common;
614
615 __be32 brdgCtl;
616
617 // P7IOC utl regs
618 __be32 portStatusReg;
619 __be32 rootCmplxStatus;
620 __be32 busAgentStatus;
621
622 // P7IOC cfg regs
623 __be32 deviceStatus;
624 __be32 slotStatus;
625 __be32 linkStatus;
626 __be32 devCmdStatus;
627 __be32 devSecStatus;
628
629 // cfg AER regs
630 __be32 rootErrorStatus;
631 __be32 uncorrErrorStatus;
632 __be32 corrErrorStatus;
633 __be32 tlpHdr1;
634 __be32 tlpHdr2;
635 __be32 tlpHdr3;
636 __be32 tlpHdr4;
637 __be32 sourceId;
638
639 __be32 rsv3;
640
641 // Record data about the call to allocate a buffer.
642 __be64 errorClass;
643 __be64 correlator;
644
645 //P7IOC MMIO Error Regs
646 __be64 p7iocPlssr; // n120
647 __be64 p7iocCsr; // n110
648 __be64 lemFir; // nC00
649 __be64 lemErrorMask; // nC18
650 __be64 lemWOF; // nC40
651 __be64 phbErrorStatus; // nC80
652 __be64 phbFirstErrorStatus; // nC88
653 __be64 phbErrorLog0; // nCC0
654 __be64 phbErrorLog1; // nCC8
655 __be64 mmioErrorStatus; // nD00
656 __be64 mmioFirstErrorStatus; // nD08
657 __be64 mmioErrorLog0; // nD40
658 __be64 mmioErrorLog1; // nD48
659 __be64 dma0ErrorStatus; // nD80
660 __be64 dma0FirstErrorStatus; // nD88
661 __be64 dma0ErrorLog0; // nDC0
662 __be64 dma0ErrorLog1; // nDC8
663 __be64 dma1ErrorStatus; // nE00
664 __be64 dma1FirstErrorStatus; // nE08
665 __be64 dma1ErrorLog0; // nE40
666 __be64 dma1ErrorLog1; // nE48
667 __be64 pestA[OPAL_P7IOC_NUM_PEST_REGS];
668 __be64 pestB[OPAL_P7IOC_NUM_PEST_REGS];
669};
670
671struct OpalIoPhb3ErrorData {
672 struct OpalIoPhbErrorCommon common;
673
674 __be32 brdgCtl;
675
676 /* PHB3 UTL regs */
677 __be32 portStatusReg;
678 __be32 rootCmplxStatus;
679 __be32 busAgentStatus;
680
681 /* PHB3 cfg regs */
682 __be32 deviceStatus;
683 __be32 slotStatus;
684 __be32 linkStatus;
685 __be32 devCmdStatus;
686 __be32 devSecStatus;
687
688 /* cfg AER regs */
689 __be32 rootErrorStatus;
690 __be32 uncorrErrorStatus;
691 __be32 corrErrorStatus;
692 __be32 tlpHdr1;
693 __be32 tlpHdr2;
694 __be32 tlpHdr3;
695 __be32 tlpHdr4;
696 __be32 sourceId;
697
698 __be32 rsv3;
699
700 /* Record data about the call to allocate a buffer */
701 __be64 errorClass;
702 __be64 correlator;
703
704 __be64 nFir; /* 000 */
705 __be64 nFirMask; /* 003 */
706 __be64 nFirWOF; /* 008 */
707
708 /* PHB3 MMIO Error Regs */
709 __be64 phbPlssr; /* 120 */
710 __be64 phbCsr; /* 110 */
711 __be64 lemFir; /* C00 */
712 __be64 lemErrorMask; /* C18 */
713 __be64 lemWOF; /* C40 */
714 __be64 phbErrorStatus; /* C80 */
715 __be64 phbFirstErrorStatus; /* C88 */
716 __be64 phbErrorLog0; /* CC0 */
717 __be64 phbErrorLog1; /* CC8 */
718 __be64 mmioErrorStatus; /* D00 */
719 __be64 mmioFirstErrorStatus; /* D08 */
720 __be64 mmioErrorLog0; /* D40 */
721 __be64 mmioErrorLog1; /* D48 */
722 __be64 dma0ErrorStatus; /* D80 */
723 __be64 dma0FirstErrorStatus; /* D88 */
724 __be64 dma0ErrorLog0; /* DC0 */
725 __be64 dma0ErrorLog1; /* DC8 */
726 __be64 dma1ErrorStatus; /* E00 */
727 __be64 dma1FirstErrorStatus; /* E08 */
728 __be64 dma1ErrorLog0; /* E40 */
729 __be64 dma1ErrorLog1; /* E48 */
730 __be64 pestA[OPAL_PHB3_NUM_PEST_REGS];
731 __be64 pestB[OPAL_PHB3_NUM_PEST_REGS];
732};
733
734enum {
735 OPAL_REINIT_CPUS_HILE_BE = (1 << 0),
736 OPAL_REINIT_CPUS_HILE_LE = (1 << 1),
737};
738
739typedef struct oppanel_line {
740 const char * line;
741 uint64_t line_len;
742} oppanel_line_t;
743
744/* OPAL I2C request */
745struct opal_i2c_request {
746 uint8_t type;
747#define OPAL_I2C_RAW_READ 0
748#define OPAL_I2C_RAW_WRITE 1
749#define OPAL_I2C_SM_READ 2
750#define OPAL_I2C_SM_WRITE 3
751 uint8_t flags;
752#define OPAL_I2C_ADDR_10 0x01 /* Not supported yet */
753 uint8_t subaddr_sz; /* Max 4 */
754 uint8_t reserved;
755 __be16 addr; /* 7 or 10 bit address */
756 __be16 reserved2;
757 __be32 subaddr; /* Sub-address if any */
758 __be32 size; /* Data size */
759 __be64 buffer_ra; /* Buffer real address */
760};
761 23
762/* /sys/firmware/opal */ 24/* /sys/firmware/opal */
763extern struct kobject *opal_kobj; 25extern struct kobject *opal_kobj;
@@ -932,6 +194,13 @@ int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
932int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id, 194int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
933 struct opal_i2c_request *oreq); 195 struct opal_i2c_request *oreq);
934 196
197int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
198 uint64_t size, uint64_t token);
199int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf,
200 uint64_t size, uint64_t token);
201int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size,
202 uint64_t token);
203
935/* Internal functions */ 204/* Internal functions */
936extern int early_init_dt_scan_opal(unsigned long node, const char *uname, 205extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
937 int depth, void *data); 206 int depth, void *data);
@@ -946,8 +215,10 @@ extern void hvc_opal_init_early(void);
946extern int opal_notifier_register(struct notifier_block *nb); 215extern int opal_notifier_register(struct notifier_block *nb);
947extern int opal_notifier_unregister(struct notifier_block *nb); 216extern int opal_notifier_unregister(struct notifier_block *nb);
948 217
949extern int opal_message_notifier_register(enum OpalMessageType msg_type, 218extern int opal_message_notifier_register(enum opal_msg_type msg_type,
950 struct notifier_block *nb); 219 struct notifier_block *nb);
220extern int opal_message_notifier_unregister(enum opal_msg_type msg_type,
221 struct notifier_block *nb);
951extern void opal_notifier_enable(void); 222extern void opal_notifier_enable(void);
952extern void opal_notifier_disable(void); 223extern void opal_notifier_disable(void);
953extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val); 224extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
@@ -962,7 +233,7 @@ extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
962struct rtc_time; 233struct rtc_time;
963extern unsigned long opal_get_boot_time(void); 234extern unsigned long opal_get_boot_time(void);
964extern void opal_nvram_init(void); 235extern void opal_nvram_init(void);
965extern void opal_flash_init(void); 236extern void opal_flash_update_init(void);
966extern void opal_flash_term_callback(void); 237extern void opal_flash_term_callback(void);
967extern int opal_elog_init(void); 238extern int opal_elog_init(void);
968extern void opal_platform_dump_init(void); 239extern void opal_platform_dump_init(void);
@@ -983,13 +254,8 @@ struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
983 unsigned long vmalloc_size); 254 unsigned long vmalloc_size);
984void opal_free_sg_list(struct opal_sg_list *sg); 255void opal_free_sg_list(struct opal_sg_list *sg);
985 256
986/* 257extern int opal_error_code(int rc);
987 * Dump region ID range usable by the OS
988 */
989#define OPAL_DUMP_REGION_HOST_START 0x80
990#define OPAL_DUMP_REGION_LOG_BUF 0x80
991#define OPAL_DUMP_REGION_HOST_END 0xFF
992 258
993#endif /* __ASSEMBLY__ */ 259#endif /* __ASSEMBLY__ */
994 260
995#endif /* __OPAL_H */ 261#endif /* _ASM_POWERPC_OPAL_H */
diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
index e5f22c6c4bf9..70bd4381f8e6 100644
--- a/arch/powerpc/include/asm/paca.h
+++ b/arch/powerpc/include/asm/paca.h
@@ -106,9 +106,9 @@ struct paca_struct {
106#endif /* CONFIG_PPC_STD_MMU_64 */ 106#endif /* CONFIG_PPC_STD_MMU_64 */
107 107
108#ifdef CONFIG_PPC_BOOK3E 108#ifdef CONFIG_PPC_BOOK3E
109 u64 exgen[8] __attribute__((aligned(0x80))); 109 u64 exgen[8] __aligned(0x40);
110 /* Keep pgd in the same cacheline as the start of extlb */ 110 /* Keep pgd in the same cacheline as the start of extlb */
111 pgd_t *pgd __attribute__((aligned(0x80))); /* Current PGD */ 111 pgd_t *pgd __aligned(0x40); /* Current PGD */
112 pgd_t *kernel_pgd; /* Kernel PGD */ 112 pgd_t *kernel_pgd; /* Kernel PGD */
113 113
114 /* Shared by all threads of a core -- points to tcd of first thread */ 114 /* Shared by all threads of a core -- points to tcd of first thread */
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 546d036fe925..1811c44bf34b 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -15,6 +15,24 @@
15struct device_node; 15struct device_node;
16 16
17/* 17/*
18 * PCI controller operations
19 */
20struct pci_controller_ops {
21 void (*dma_dev_setup)(struct pci_dev *dev);
22 void (*dma_bus_setup)(struct pci_bus *bus);
23
24 int (*probe_mode)(struct pci_bus *);
25
26 /* Called when pci_enable_device() is called. Returns true to
27 * allow assignment/enabling of the device. */
28 bool (*enable_device_hook)(struct pci_dev *);
29
30 /* Called during PCI resource reassignment */
31 resource_size_t (*window_alignment)(struct pci_bus *, unsigned long type);
32 void (*reset_secondary_bus)(struct pci_dev *dev);
33};
34
35/*
18 * Structure of a PCI controller (host bridge) 36 * Structure of a PCI controller (host bridge)
19 */ 37 */
20struct pci_controller { 38struct pci_controller {
@@ -46,6 +64,7 @@ struct pci_controller {
46 resource_size_t isa_mem_phys; 64 resource_size_t isa_mem_phys;
47 resource_size_t isa_mem_size; 65 resource_size_t isa_mem_size;
48 66
67 struct pci_controller_ops controller_ops;
49 struct pci_ops *ops; 68 struct pci_ops *ops;
50 unsigned int __iomem *cfg_addr; 69 unsigned int __iomem *cfg_addr;
51 void __iomem *cfg_data; 70 void __iomem *cfg_data;
@@ -89,6 +108,7 @@ struct pci_controller {
89 108
90#ifdef CONFIG_PPC64 109#ifdef CONFIG_PPC64
91 unsigned long buid; 110 unsigned long buid;
111 struct pci_dn *pci_data;
92#endif /* CONFIG_PPC64 */ 112#endif /* CONFIG_PPC64 */
93 113
94 void *private_data; 114 void *private_data;
@@ -154,31 +174,51 @@ static inline int isa_vaddr_is_ioport(void __iomem *address)
154struct iommu_table; 174struct iommu_table;
155 175
156struct pci_dn { 176struct pci_dn {
177 int flags;
178#define PCI_DN_FLAG_IOV_VF 0x01
179
157 int busno; /* pci bus number */ 180 int busno; /* pci bus number */
158 int devfn; /* pci device and function number */ 181 int devfn; /* pci device and function number */
182 int vendor_id; /* Vendor ID */
183 int device_id; /* Device ID */
184 int class_code; /* Device class code */
159 185
186 struct pci_dn *parent;
160 struct pci_controller *phb; /* for pci devices */ 187 struct pci_controller *phb; /* for pci devices */
161 struct iommu_table *iommu_table; /* for phb's or bridges */ 188 struct iommu_table *iommu_table; /* for phb's or bridges */
162 struct device_node *node; /* back-pointer to the device_node */ 189 struct device_node *node; /* back-pointer to the device_node */
163 190
164 int pci_ext_config_space; /* for pci devices */ 191 int pci_ext_config_space; /* for pci devices */
165 192
166 struct pci_dev *pcidev; /* back-pointer to the pci device */
167#ifdef CONFIG_EEH 193#ifdef CONFIG_EEH
168 struct eeh_dev *edev; /* eeh device */ 194 struct eeh_dev *edev; /* eeh device */
169#endif 195#endif
170#define IODA_INVALID_PE (-1) 196#define IODA_INVALID_PE (-1)
171#ifdef CONFIG_PPC_POWERNV 197#ifdef CONFIG_PPC_POWERNV
172 int pe_number; 198 int pe_number;
199#ifdef CONFIG_PCI_IOV
200 u16 vfs_expanded; /* number of VFs IOV BAR expanded */
201 u16 num_vfs; /* number of VFs enabled*/
202 int offset; /* PE# for the first VF PE */
203#define M64_PER_IOV 4
204 int m64_per_iov;
205#define IODA_INVALID_M64 (-1)
206 int m64_wins[PCI_SRIOV_NUM_BARS][M64_PER_IOV];
207#endif /* CONFIG_PCI_IOV */
173#endif 208#endif
209 struct list_head child_list;
210 struct list_head list;
174}; 211};
175 212
176/* Get the pointer to a device_node's pci_dn */ 213/* Get the pointer to a device_node's pci_dn */
177#define PCI_DN(dn) ((struct pci_dn *) (dn)->data) 214#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
178 215
216extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
217 int devfn);
179extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev); 218extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
180 219extern struct pci_dn *add_dev_pci_data(struct pci_dev *pdev);
181extern void * update_dn_pci_info(struct device_node *dn, void *data); 220extern void remove_dev_pci_data(struct pci_dev *pdev);
221extern void *update_dn_pci_info(struct device_node *dn, void *data);
182 222
183static inline int pci_device_from_OF_node(struct device_node *np, 223static inline int pci_device_from_OF_node(struct device_node *np,
184 u8 *bus, u8 *devfn) 224 u8 *bus, u8 *devfn)
@@ -191,20 +231,12 @@ static inline int pci_device_from_OF_node(struct device_node *np,
191} 231}
192 232
193#if defined(CONFIG_EEH) 233#if defined(CONFIG_EEH)
194static inline struct eeh_dev *of_node_to_eeh_dev(struct device_node *dn) 234static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
195{ 235{
196 /* 236 return pdn ? pdn->edev : NULL;
197 * For those OF nodes whose parent isn't PCI bridge, they
198 * don't have PCI_DN actually. So we have to skip them for
199 * any EEH operations.
200 */
201 if (!dn || !PCI_DN(dn))
202 return NULL;
203
204 return PCI_DN(dn)->edev;
205} 237}
206#else 238#else
207#define of_node_to_eeh_dev(x) (NULL) 239#define pdn_to_eeh_dev(x) (NULL)
208#endif 240#endif
209 241
210/** Find the bus corresponding to the indicated device node */ 242/** Find the bus corresponding to the indicated device node */
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index 1b0739bc14b5..4aef8d660999 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -22,7 +22,7 @@
22 22
23#include <asm-generic/pci-dma-compat.h> 23#include <asm-generic/pci-dma-compat.h>
24 24
25/* Return values for ppc_md.pci_probe_mode function */ 25/* Return values for pci_controller_ops.probe_mode function */
26#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */ 26#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
27#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */ 27#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
28#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */ 28#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
diff --git a/arch/powerpc/include/asm/ppc-pci.h b/arch/powerpc/include/asm/ppc-pci.h
index db1e2b8eff3c..4122a86d6858 100644
--- a/arch/powerpc/include/asm/ppc-pci.h
+++ b/arch/powerpc/include/asm/ppc-pci.h
@@ -23,8 +23,6 @@ extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary);
23 23
24extern struct list_head hose_list; 24extern struct list_head hose_list;
25 25
26extern void find_and_init_phbs(void);
27
28extern struct pci_dev *isa_bridge_pcidev; /* may be NULL if no ISA bus */ 26extern struct pci_dev *isa_bridge_pcidev; /* may be NULL if no ISA bus */
29 27
30/** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */ 28/** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */
@@ -33,9 +31,14 @@ extern struct pci_dev *isa_bridge_pcidev; /* may be NULL if no ISA bus */
33 31
34/* PCI device_node operations */ 32/* PCI device_node operations */
35struct device_node; 33struct device_node;
34struct pci_dn;
35
36typedef void *(*traverse_func)(struct device_node *me, void *data); 36typedef void *(*traverse_func)(struct device_node *me, void *data);
37void *traverse_pci_devices(struct device_node *start, traverse_func pre, 37void *traverse_pci_devices(struct device_node *start, traverse_func pre,
38 void *data); 38 void *data);
39void *traverse_pci_dn(struct pci_dn *root,
40 void *(*fn)(struct pci_dn *, void *),
41 void *data);
39 42
40extern void pci_devs_phb_init(void); 43extern void pci_devs_phb_init(void);
41extern void pci_devs_phb_init_dynamic(struct pci_controller *phb); 44extern void pci_devs_phb_init_dynamic(struct pci_controller *phb);
@@ -76,7 +79,6 @@ static inline const char *eeh_driver_name(struct pci_dev *pdev)
76#endif /* CONFIG_EEH */ 79#endif /* CONFIG_EEH */
77 80
78#else /* CONFIG_PCI */ 81#else /* CONFIG_PCI */
79static inline void find_and_init_phbs(void) { }
80static inline void init_pci_config_tokens(void) { } 82static inline void init_pci_config_tokens(void) { }
81#endif /* !CONFIG_PCI */ 83#endif /* !CONFIG_PCI */
82 84
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h
index 7e4612528546..dd0fc18d8103 100644
--- a/arch/powerpc/include/asm/ppc_asm.h
+++ b/arch/powerpc/include/asm/ppc_asm.h
@@ -637,105 +637,105 @@ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,945)
637 637
638/* AltiVec Registers (VPRs) */ 638/* AltiVec Registers (VPRs) */
639 639
640#define vr0 0 640#define v0 0
641#define vr1 1 641#define v1 1
642#define vr2 2 642#define v2 2
643#define vr3 3 643#define v3 3
644#define vr4 4 644#define v4 4
645#define vr5 5 645#define v5 5
646#define vr6 6 646#define v6 6
647#define vr7 7 647#define v7 7
648#define vr8 8 648#define v8 8
649#define vr9 9 649#define v9 9
650#define vr10 10 650#define v10 10
651#define vr11 11 651#define v11 11
652#define vr12 12 652#define v12 12
653#define vr13 13 653#define v13 13
654#define vr14 14 654#define v14 14
655#define vr15 15 655#define v15 15
656#define vr16 16 656#define v16 16
657#define vr17 17 657#define v17 17
658#define vr18 18 658#define v18 18
659#define vr19 19 659#define v19 19
660#define vr20 20 660#define v20 20
661#define vr21 21 661#define v21 21
662#define vr22 22 662#define v22 22
663#define vr23 23 663#define v23 23
664#define vr24 24 664#define v24 24
665#define vr25 25 665#define v25 25
666#define vr26 26 666#define v26 26
667#define vr27 27 667#define v27 27
668#define vr28 28 668#define v28 28
669#define vr29 29 669#define v29 29
670#define vr30 30 670#define v30 30
671#define vr31 31 671#define v31 31
672 672
673/* VSX Registers (VSRs) */ 673/* VSX Registers (VSRs) */
674 674
675#define vsr0 0 675#define vs0 0
676#define vsr1 1 676#define vs1 1
677#define vsr2 2 677#define vs2 2
678#define vsr3 3 678#define vs3 3
679#define vsr4 4 679#define vs4 4
680#define vsr5 5 680#define vs5 5
681#define vsr6 6 681#define vs6 6
682#define vsr7 7 682#define vs7 7
683#define vsr8 8 683#define vs8 8
684#define vsr9 9 684#define vs9 9
685#define vsr10 10 685#define vs10 10
686#define vsr11 11 686#define vs11 11
687#define vsr12 12 687#define vs12 12
688#define vsr13 13 688#define vs13 13
689#define vsr14 14 689#define vs14 14
690#define vsr15 15 690#define vs15 15
691#define vsr16 16 691#define vs16 16
692#define vsr17 17 692#define vs17 17
693#define vsr18 18 693#define vs18 18
694#define vsr19 19 694#define vs19 19
695#define vsr20 20 695#define vs20 20
696#define vsr21 21 696#define vs21 21
697#define vsr22 22 697#define vs22 22
698#define vsr23 23 698#define vs23 23
699#define vsr24 24 699#define vs24 24
700#define vsr25 25 700#define vs25 25
701#define vsr26 26 701#define vs26 26
702#define vsr27 27 702#define vs27 27
703#define vsr28 28 703#define vs28 28
704#define vsr29 29 704#define vs29 29
705#define vsr30 30 705#define vs30 30
706#define vsr31 31 706#define vs31 31
707#define vsr32 32 707#define vs32 32
708#define vsr33 33 708#define vs33 33
709#define vsr34 34 709#define vs34 34
710#define vsr35 35 710#define vs35 35
711#define vsr36 36 711#define vs36 36
712#define vsr37 37 712#define vs37 37
713#define vsr38 38 713#define vs38 38
714#define vsr39 39 714#define vs39 39
715#define vsr40 40 715#define vs40 40
716#define vsr41 41 716#define vs41 41
717#define vsr42 42 717#define vs42 42
718#define vsr43 43 718#define vs43 43
719#define vsr44 44 719#define vs44 44
720#define vsr45 45 720#define vs45 45
721#define vsr46 46 721#define vs46 46
722#define vsr47 47 722#define vs47 47
723#define vsr48 48 723#define vs48 48
724#define vsr49 49 724#define vs49 49
725#define vsr50 50 725#define vs50 50
726#define vsr51 51 726#define vs51 51
727#define vsr52 52 727#define vs52 52
728#define vsr53 53 728#define vs53 53
729#define vsr54 54 729#define vs54 54
730#define vsr55 55 730#define vs55 55
731#define vsr56 56 731#define vs56 56
732#define vsr57 57 732#define vs57 57
733#define vsr58 58 733#define vs58 58
734#define vsr59 59 734#define vs59 59
735#define vsr60 60 735#define vs60 60
736#define vsr61 61 736#define vs61 61
737#define vsr62 62 737#define vs62 62
738#define vsr63 63 738#define vs63 63
739 739
740/* SPE Registers (EVPRs) */ 740/* SPE Registers (EVPRs) */
741 741
diff --git a/arch/powerpc/include/asm/rtas.h b/arch/powerpc/include/asm/rtas.h
index 2e23e92a4372..7a4ede16b283 100644
--- a/arch/powerpc/include/asm/rtas.h
+++ b/arch/powerpc/include/asm/rtas.h
@@ -4,6 +4,7 @@
4 4
5#include <linux/spinlock.h> 5#include <linux/spinlock.h>
6#include <asm/page.h> 6#include <asm/page.h>
7#include <linux/time.h>
7 8
8/* 9/*
9 * Definitions for talking to the RTAS on CHRP machines. 10 * Definitions for talking to the RTAS on CHRP machines.
@@ -273,6 +274,7 @@ inline uint32_t rtas_ext_event_company_id(struct rtas_ext_event_log_v6 *ext_log)
273#define PSERIES_ELOG_SECT_ID_MANUFACT_INFO (('M' << 8) | 'I') 274#define PSERIES_ELOG_SECT_ID_MANUFACT_INFO (('M' << 8) | 'I')
274#define PSERIES_ELOG_SECT_ID_CALL_HOME (('C' << 8) | 'H') 275#define PSERIES_ELOG_SECT_ID_CALL_HOME (('C' << 8) | 'H')
275#define PSERIES_ELOG_SECT_ID_USER_DEF (('U' << 8) | 'D') 276#define PSERIES_ELOG_SECT_ID_USER_DEF (('U' << 8) | 'D')
277#define PSERIES_ELOG_SECT_ID_HOTPLUG (('H' << 8) | 'P')
276 278
277/* Vendor specific Platform Event Log Format, Version 6, section header */ 279/* Vendor specific Platform Event Log Format, Version 6, section header */
278struct pseries_errorlog { 280struct pseries_errorlog {
@@ -296,6 +298,31 @@ inline uint16_t pseries_errorlog_length(struct pseries_errorlog *sect)
296 return be16_to_cpu(sect->length); 298 return be16_to_cpu(sect->length);
297} 299}
298 300
301/* RTAS pseries hotplug errorlog section */
302struct pseries_hp_errorlog {
303 u8 resource;
304 u8 action;
305 u8 id_type;
306 u8 reserved;
307 union {
308 __be32 drc_index;
309 __be32 drc_count;
310 char drc_name[1];
311 } _drc_u;
312};
313
314#define PSERIES_HP_ELOG_RESOURCE_CPU 1
315#define PSERIES_HP_ELOG_RESOURCE_MEM 2
316#define PSERIES_HP_ELOG_RESOURCE_SLOT 3
317#define PSERIES_HP_ELOG_RESOURCE_PHB 4
318
319#define PSERIES_HP_ELOG_ACTION_ADD 1
320#define PSERIES_HP_ELOG_ACTION_REMOVE 2
321
322#define PSERIES_HP_ELOG_ID_DRC_NAME 1
323#define PSERIES_HP_ELOG_ID_DRC_INDEX 2
324#define PSERIES_HP_ELOG_ID_DRC_COUNT 3
325
299struct pseries_errorlog *get_pseries_errorlog(struct rtas_error_log *log, 326struct pseries_errorlog *get_pseries_errorlog(struct rtas_error_log *log,
300 uint16_t section_id); 327 uint16_t section_id);
301 328
@@ -327,7 +354,7 @@ extern int rtas_suspend_cpu(struct rtas_suspend_me_data *data);
327extern int rtas_suspend_last_cpu(struct rtas_suspend_me_data *data); 354extern int rtas_suspend_last_cpu(struct rtas_suspend_me_data *data);
328extern int rtas_online_cpus_mask(cpumask_var_t cpus); 355extern int rtas_online_cpus_mask(cpumask_var_t cpus);
329extern int rtas_offline_cpus_mask(cpumask_var_t cpus); 356extern int rtas_offline_cpus_mask(cpumask_var_t cpus);
330extern int rtas_ibm_suspend_me(u64 handle, int *vasi_return); 357extern int rtas_ibm_suspend_me(u64 handle);
331 358
332struct rtc_time; 359struct rtc_time;
333extern unsigned long rtas_get_boot_time(void); 360extern unsigned long rtas_get_boot_time(void);
@@ -343,8 +370,12 @@ extern int early_init_dt_scan_rtas(unsigned long node,
343extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal); 370extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
344 371
345#ifdef CONFIG_PPC_PSERIES 372#ifdef CONFIG_PPC_PSERIES
373extern time64_t last_rtas_event;
374extern int clobbering_unread_rtas_event(void);
346extern int pseries_devicetree_update(s32 scope); 375extern int pseries_devicetree_update(s32 scope);
347extern void post_mobility_fixup(void); 376extern void post_mobility_fixup(void);
377#else
378static inline int clobbering_unread_rtas_event(void) { return 0; }
348#endif 379#endif
349 380
350#ifdef CONFIG_PPC_RTAS_DAEMON 381#ifdef CONFIG_PPC_RTAS_DAEMON
diff --git a/arch/powerpc/include/asm/setup.h b/arch/powerpc/include/asm/setup.h
index fbdf18cf954c..e9d384cbd021 100644
--- a/arch/powerpc/include/asm/setup.h
+++ b/arch/powerpc/include/asm/setup.h
@@ -7,7 +7,6 @@
7extern void ppc_printk_progress(char *s, unsigned short hex); 7extern void ppc_printk_progress(char *s, unsigned short hex);
8 8
9extern unsigned int rtas_data; 9extern unsigned int rtas_data;
10extern int mem_init_done; /* set on boot once kmalloc can be called */
11extern unsigned long long memory_limit; 10extern unsigned long long memory_limit;
12extern unsigned long klimit; 11extern unsigned long klimit;
13extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask); 12extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
diff --git a/arch/powerpc/include/asm/smp.h b/arch/powerpc/include/asm/smp.h
index d607df5081a7..825663c30945 100644
--- a/arch/powerpc/include/asm/smp.h
+++ b/arch/powerpc/include/asm/smp.h
@@ -42,7 +42,7 @@ struct smp_ops_t {
42#ifdef CONFIG_PPC_SMP_MUXED_IPI 42#ifdef CONFIG_PPC_SMP_MUXED_IPI
43 void (*cause_ipi)(int cpu, unsigned long data); 43 void (*cause_ipi)(int cpu, unsigned long data);
44#endif 44#endif
45 int (*probe)(void); 45 void (*probe)(void);
46 int (*kick_cpu)(int nr); 46 int (*kick_cpu)(int nr);
47 void (*setup_cpu)(int nr); 47 void (*setup_cpu)(int nr);
48 void (*bringup_done)(void); 48 void (*bringup_done)(void);
@@ -125,7 +125,6 @@ extern irqreturn_t smp_ipi_demux(void);
125 125
126void smp_init_pSeries(void); 126void smp_init_pSeries(void);
127void smp_init_cell(void); 127void smp_init_cell(void);
128void smp_init_celleb(void);
129void smp_setup_cpu_maps(void); 128void smp_setup_cpu_maps(void);
130 129
131extern int __cpu_disable(void); 130extern int __cpu_disable(void);
@@ -175,7 +174,7 @@ static inline void set_hard_smp_processor_id(int cpu, int phys)
175 174
176extern int smt_enabled_at_boot; 175extern int smt_enabled_at_boot;
177 176
178extern int smp_mpic_probe(void); 177extern void smp_mpic_probe(void);
179extern void smp_mpic_setup_cpu(int cpu); 178extern void smp_mpic_setup_cpu(int cpu);
180extern int smp_generic_kick_cpu(int nr); 179extern int smp_generic_kick_cpu(int nr);
181extern int smp_generic_cpu_bootable(unsigned int nr); 180extern int smp_generic_cpu_bootable(unsigned int nr);
diff --git a/arch/powerpc/include/asm/swab.h b/arch/powerpc/include/asm/swab.h
index 96f59de61855..487e09077a3e 100644
--- a/arch/powerpc/include/asm/swab.h
+++ b/arch/powerpc/include/asm/swab.h
@@ -9,30 +9,4 @@
9 9
10#include <uapi/asm/swab.h> 10#include <uapi/asm/swab.h>
11 11
12static __inline__ __u16 ld_le16(const volatile __u16 *addr)
13{
14 __u16 val;
15
16 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
17 return val;
18}
19
20static __inline__ void st_le16(volatile __u16 *addr, const __u16 val)
21{
22 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
23}
24
25static __inline__ __u32 ld_le32(const volatile __u32 *addr)
26{
27 __u32 val;
28
29 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
30 return val;
31}
32
33static __inline__ void st_le32(volatile __u32 *addr, const __u32 val)
34{
35 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
36}
37
38#endif /* _ASM_POWERPC_SWAB_H */ 12#endif /* _ASM_POWERPC_SWAB_H */
diff --git a/arch/powerpc/include/asm/systbl.h b/arch/powerpc/include/asm/systbl.h
index 91062eef582f..f1863a138b4a 100644
--- a/arch/powerpc/include/asm/systbl.h
+++ b/arch/powerpc/include/asm/systbl.h
@@ -367,3 +367,4 @@ SYSCALL_SPU(getrandom)
367SYSCALL_SPU(memfd_create) 367SYSCALL_SPU(memfd_create)
368SYSCALL_SPU(bpf) 368SYSCALL_SPU(bpf)
369COMPAT_SYS(execveat) 369COMPAT_SYS(execveat)
370PPC64ONLY(switch_endian)
diff --git a/arch/powerpc/include/asm/ucc_slow.h b/arch/powerpc/include/asm/ucc_slow.h
index c44131e68e11..233ef5fe5fde 100644
--- a/arch/powerpc/include/asm/ucc_slow.h
+++ b/arch/powerpc/include/asm/ucc_slow.h
@@ -251,19 +251,6 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode);
251 */ 251 */
252void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode); 252void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode);
253 253
254/* ucc_slow_poll_transmitter_now
255 * Immediately forces a poll of the transmitter for data to be sent.
256 * Typically, the hardware performs a periodic poll for data that the
257 * transmit routine has set up to be transmitted. In cases where
258 * this polling cycle is not soon enough, this optional routine can
259 * be invoked to force a poll right away, instead. Proper use for
260 * each transmission for which this functionality is desired is to
261 * call the transmit routine and then this routine right after.
262 *
263 * uccs - (In) pointer to the slow UCC structure.
264 */
265void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs);
266
267/* ucc_slow_graceful_stop_tx 254/* ucc_slow_graceful_stop_tx
268 * Smoothly stops transmission on a specified slow UCC. 255 * Smoothly stops transmission on a specified slow UCC.
269 * 256 *
diff --git a/arch/powerpc/include/asm/unistd.h b/arch/powerpc/include/asm/unistd.h
index 36b79c31eedd..f4f8b667d75b 100644
--- a/arch/powerpc/include/asm/unistd.h
+++ b/arch/powerpc/include/asm/unistd.h
@@ -12,7 +12,7 @@
12#include <uapi/asm/unistd.h> 12#include <uapi/asm/unistd.h>
13 13
14 14
15#define __NR_syscalls 363 15#define __NR_syscalls 364
16 16
17#define __NR__exit __NR_exit 17#define __NR__exit __NR_exit
18#define NR_syscalls __NR_syscalls 18#define NR_syscalls __NR_syscalls
diff --git a/arch/powerpc/include/asm/vga.h b/arch/powerpc/include/asm/vga.h
index e5f8dd366212..ab3acd2f2786 100644
--- a/arch/powerpc/include/asm/vga.h
+++ b/arch/powerpc/include/asm/vga.h
@@ -25,12 +25,12 @@
25 25
26static inline void scr_writew(u16 val, volatile u16 *addr) 26static inline void scr_writew(u16 val, volatile u16 *addr)
27{ 27{
28 st_le16(addr, val); 28 *addr = cpu_to_le16(val);
29} 29}
30 30
31static inline u16 scr_readw(volatile const u16 *addr) 31static inline u16 scr_readw(volatile const u16 *addr)
32{ 32{
33 return ld_le16(addr); 33 return le16_to_cpu(*addr);
34} 34}
35 35
36#define VT_BUF_HAVE_MEMCPYW 36#define VT_BUF_HAVE_MEMCPYW
diff --git a/arch/powerpc/include/asm/xics.h b/arch/powerpc/include/asm/xics.h
index 6997f4a271df..0e25bdb190bb 100644
--- a/arch/powerpc/include/asm/xics.h
+++ b/arch/powerpc/include/asm/xics.h
@@ -146,7 +146,7 @@ extern void xics_update_irq_servers(void);
146extern void xics_set_cpu_giq(unsigned int gserver, unsigned int join); 146extern void xics_set_cpu_giq(unsigned int gserver, unsigned int join);
147extern void xics_mask_unknown_vec(unsigned int vec); 147extern void xics_mask_unknown_vec(unsigned int vec);
148extern irqreturn_t xics_ipi_dispatch(int cpu); 148extern irqreturn_t xics_ipi_dispatch(int cpu);
149extern int xics_smp_probe(void); 149extern void xics_smp_probe(void);
150extern void xics_register_ics(struct ics *ics); 150extern void xics_register_ics(struct ics *ics);
151extern void xics_teardown_cpu(void); 151extern void xics_teardown_cpu(void);
152extern void xics_kexec_teardown_cpu(int secondary); 152extern void xics_kexec_teardown_cpu(int secondary);
diff --git a/arch/powerpc/include/uapi/asm/ptrace.h b/arch/powerpc/include/uapi/asm/ptrace.h
index 77d2ed35b111..8036b385417d 100644
--- a/arch/powerpc/include/uapi/asm/ptrace.h
+++ b/arch/powerpc/include/uapi/asm/ptrace.h
@@ -136,7 +136,7 @@ struct pt_regs {
136#endif /* __powerpc64__ */ 136#endif /* __powerpc64__ */
137 137
138/* 138/*
139 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go. 139 * Get/set all the altivec registers v0..v31, vscr, vrsave, in one go.
140 * The transfer totals 34 quadword. Quadwords 0-31 contain the 140 * The transfer totals 34 quadword. Quadwords 0-31 contain the
141 * corresponding vector registers. Quadword 32 contains the vscr as the 141 * corresponding vector registers. Quadword 32 contains the vscr as the
142 * last word (offset 12) within that quadword. Quadword 33 contains the 142 * last word (offset 12) within that quadword. Quadword 33 contains the
diff --git a/arch/powerpc/include/uapi/asm/tm.h b/arch/powerpc/include/uapi/asm/tm.h
index 5d836b7c1176..5047659815a5 100644
--- a/arch/powerpc/include/uapi/asm/tm.h
+++ b/arch/powerpc/include/uapi/asm/tm.h
@@ -11,7 +11,7 @@
11#define TM_CAUSE_RESCHED 0xde 11#define TM_CAUSE_RESCHED 0xde
12#define TM_CAUSE_TLBI 0xdc 12#define TM_CAUSE_TLBI 0xdc
13#define TM_CAUSE_FAC_UNAV 0xda 13#define TM_CAUSE_FAC_UNAV 0xda
14#define TM_CAUSE_SYSCALL 0xd8 /* future use */ 14#define TM_CAUSE_SYSCALL 0xd8
15#define TM_CAUSE_MISC 0xd6 /* future use */ 15#define TM_CAUSE_MISC 0xd6 /* future use */
16#define TM_CAUSE_SIGNAL 0xd4 16#define TM_CAUSE_SIGNAL 0xd4
17#define TM_CAUSE_ALIGNMENT 0xd2 17#define TM_CAUSE_ALIGNMENT 0xd2
diff --git a/arch/powerpc/include/uapi/asm/unistd.h b/arch/powerpc/include/uapi/asm/unistd.h
index ef5b5b1f3123..e4aa173dae62 100644
--- a/arch/powerpc/include/uapi/asm/unistd.h
+++ b/arch/powerpc/include/uapi/asm/unistd.h
@@ -385,5 +385,6 @@
385#define __NR_memfd_create 360 385#define __NR_memfd_create 360
386#define __NR_bpf 361 386#define __NR_bpf 361
387#define __NR_execveat 362 387#define __NR_execveat 362
388#define __NR_switch_endian 363
388 389
389#endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */ 390#endif /* _UAPI_ASM_POWERPC_UNISTD_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-18 06:55:25 -0500