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authorAnton Blanchard <anton@samba.org>2012-04-10 12:22:12 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2012-04-30 01:37:16 -0400
commit448054a6508d74767ba4c76654b42182e4f750b6 (patch)
tree3ad062adab07797e5fedb610aa80386c316da897 /arch/powerpc/include
parentcf8a056a2226754087320541fb4de743cc81cd2e (diff)
powerpc: Remove iseries specific fields in lppaca
Remove all the iseries specific fields in the lppaca. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/lppaca.h70
1 files changed, 12 insertions, 58 deletions
diff --git a/arch/powerpc/include/asm/lppaca.h b/arch/powerpc/include/asm/lppaca.h
index bc4e37552948..06effe61a0de 100644
--- a/arch/powerpc/include/asm/lppaca.h
+++ b/arch/powerpc/include/asm/lppaca.h
@@ -28,7 +28,7 @@
28//============================================================================= 28//=============================================================================
29// 29//
30// This control block contains the data that is shared between the 30// This control block contains the data that is shared between the
31// hypervisor (PLIC) and the OS. 31// hypervisor and the OS.
32// 32//
33// 33//
34//---------------------------------------------------------------------------- 34//----------------------------------------------------------------------------
@@ -49,9 +49,6 @@
49struct lppaca { 49struct lppaca {
50//============================================================================= 50//=============================================================================
51// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data 51// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
52// NOTE: The xDynXyz fields are fields that will be dynamically changed by
53// PLIC when preparing to bring a processor online or when dispatching a
54// virtual processor!
55//============================================================================= 52//=============================================================================
56 u32 desc; // Eye catcher 0xD397D781 x00-x03 53 u32 desc; // Eye catcher 0xD397D781 x00-x03
57 u16 size; // Size of this struct x04-x05 54 u16 size; // Size of this struct x04-x05
@@ -59,75 +56,32 @@ struct lppaca {
59 u16 reserved2:14; // Reserved x08-x09 56 u16 reserved2:14; // Reserved x08-x09
60 u8 shared_proc:1; // Shared processor indicator ... 57 u8 shared_proc:1; // Shared processor indicator ...
61 u8 secondary_thread:1; // Secondary thread indicator ... 58 u8 secondary_thread:1; // Secondary thread indicator ...
62 volatile u8 dyn_proc_status:8; // Dynamic Status of this proc x0A-x0A 59 u8 reserved3[14]; // x0A-x17
63 u8 secondary_thread_count; // Secondary thread count x0B-x0B
64 volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D
65 volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F
66 u32 decr_val; // Value for Decr programming x10-x13
67 u32 pmc_val; // Value for PMC regs x14-x17
68 volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B 60 volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B
69 volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F 61 volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F
70 volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23 62 u8 reserved4[56]; // Reserved x20-x57
71 u32 dsei_data; // DSEI data x24-x27
72 u64 sprg3; // SPRG3 value x28-x2F
73 u8 reserved3[40]; // Reserved x30-x57
74 volatile u8 vphn_assoc_counts[8]; // Virtual processor home node 63 volatile u8 vphn_assoc_counts[8]; // Virtual processor home node
75 // associativity change counters x58-x5F 64 // associativity change counters x58-x5F
76 u8 reserved4[32]; // Reserved x60-x7F 65 u8 reserved5[32]; // Reserved x60-x7F
77 66
78//============================================================================= 67//=============================================================================
79// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data 68// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
80//============================================================================= 69//=============================================================================
81 // This Dword contains a byte for each type of interrupt that can occur. 70
82 // The IPI is a count while the others are just a binary 1 or 0. 71 u8 reserved6[48]; // x00-x2f
83 union {
84 u64 any_int;
85 struct {
86 u16 reserved; // Reserved - cleared by #mpasmbl
87 u8 xirr_int; // Indicates xXirrValue is valid or Immed IO
88 u8 ipi_cnt; // IPI Count
89 u8 decr_int; // DECR interrupt occurred
90 u8 pdc_int; // PDC interrupt occurred
91 u8 quantum_int; // Interrupt quantum reached
92 u8 old_plic_deferred_ext_int; // Old PLIC has a deferred XIRR pending
93 } fields;
94 } int_dword;
95
96 // Whenever any fields in this Dword are set then PLIC will defer the
97 // processing of external interrupts. Note that PLIC will store the
98 // XIRR directly into the xXirrValue field so that another XIRR will
99 // not be presented until this one clears. The layout of the low
100 // 4-bytes of this Dword is up to SLIC - PLIC just checks whether the
101 // entire Dword is zero or not. A non-zero value in the low order
102 // 2-bytes will result in SLIC being granted the highest thread
103 // priority upon return. A 0 will return to SLIC as medium priority.
104 u64 plic_defer_ints_area; // Entire Dword
105
106 // Used to pass the real SRR0/1 from PLIC to SLIC as well as to
107 // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
108 u64 saved_srr0; // Saved SRR0 x10-x17
109 u64 saved_srr1; // Saved SRR1 x18-x1F
110 u64 reserved5[2]; /* x20-x2F */
111 u8 cede_latency_hint; /* x30 */ 72 u8 cede_latency_hint; /* x30 */
112 u8 reserved[7]; /* x31-x37 */ 73 u8 reserved7[7]; /* x31-x37 */
113 u8 dtl_enable_mask; // Dispatch Trace Log mask x38-x38 74 u8 dtl_enable_mask; // Dispatch Trace Log mask x38-x38
114 u8 donate_dedicated_cpu; // Donate dedicated CPU cycles x39-x39 75 u8 donate_dedicated_cpu; // Donate dedicated CPU cycles x39-x39
115 u8 fpregs_in_use; // FP regs in use x3A-x3A 76 u8 fpregs_in_use; // FP regs in use x3A-x3A
116 u8 pmcregs_in_use; // PMC regs in use x3B-x3B 77 u8 pmcregs_in_use; // PMC regs in use x3B-x3B
117 volatile u32 saved_decr; // Saved Decr Value x3C-x3F 78 u8 reserved8[28]; // x3C-x57
118 volatile u64 emulated_time_base;// Emulated TB for this thread x40-x47
119 volatile u64 cur_plic_latency; // Unaccounted PLIC latency x48-x4F
120 u64 tot_plic_latency; // Accumulated PLIC latency x50-x57
121 u64 wait_state_cycles; // Wait cycles for this proc x58-x5F 79 u64 wait_state_cycles; // Wait cycles for this proc x58-x5F
122 u64 end_of_quantum; // TB at end of quantum x60-x67 80 u8 reserved9[28]; // x60-x7B
123 u64 pdc_saved_sprg1; // Saved SPRG1 for PMC int x68-x6F
124 u64 pdc_saved_srr0; // Saved SRR0 for PMC int x70-x77
125 volatile u32 virtual_decr; // Virtual DECR for shared procsx78-x7B
126 u16 slb_count; // # of SLBs to maintain x7C-x7D 81 u16 slb_count; // # of SLBs to maintain x7C-x7D
127 u8 idle; // Indicate OS is idle x7E 82 u8 idle; // Indicate OS is idle x7E
128 u8 vmxregs_in_use; // VMX registers in use x7F 83 u8 vmxregs_in_use; // VMX registers in use x7F
129 84
130
131//============================================================================= 85//=============================================================================
132// CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors 86// CACHE_LINE_3 0x0100 - 0x017F: This line is shared with other processors
133//============================================================================= 87//=============================================================================
@@ -141,15 +95,15 @@ struct lppaca {
141 volatile u32 dispersion_count; // dispatch changed phys cpu x04-x07 95 volatile u32 dispersion_count; // dispatch changed phys cpu x04-x07
142 volatile u64 cmo_faults; // CMO page fault count x08-x0F 96 volatile u64 cmo_faults; // CMO page fault count x08-x0F
143 volatile u64 cmo_fault_time; // CMO page fault time x10-x17 97 volatile u64 cmo_fault_time; // CMO page fault time x10-x17
144 u8 reserved7[104]; // Reserved x18-x7F 98 u8 reserved10[104]; // Reserved x18-x7F
145 99
146//============================================================================= 100//=============================================================================
147// CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data 101// CACHE_LINE_4-5 0x0180 - 0x027F Contains PMC interrupt data
148//============================================================================= 102//=============================================================================
149 u32 page_ins; // CMO Hint - # page ins by OS x00-x03 103 u32 page_ins; // CMO Hint - # page ins by OS x00-x03
150 u8 reserved8[148]; // Reserved x04-x97 104 u8 reserved11[148]; // Reserved x04-x97
151 volatile u64 dtl_idx; // Dispatch Trace Log head idx x98-x9F 105 volatile u64 dtl_idx; // Dispatch Trace Log head idx x98-x9F
152 u8 reserved9[96]; // Reserved xA0-xFF 106 u8 reserved12[96]; // Reserved xA0-xFF
153} __attribute__((__aligned__(0x400))); 107} __attribute__((__aligned__(0x400)));
154 108
155extern struct lppaca lppaca[]; 109extern struct lppaca lppaca[];
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