diff options
author | Nate Case <ncase@xes-inc.com> | 2009-06-10 16:37:28 -0400 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2009-06-15 22:45:30 -0400 |
commit | cab888e678d0986ebce95464d3842a6aeca1e3d8 (patch) | |
tree | e6ead4aac68d3a1b694c1cfed56b4650a1ab8715 /arch/powerpc/include | |
parent | c7a7a5b9a27e28ce5f800ead9091ce68d37e8088 (diff) |
powerpc/fsl-booke: Enable L1 cache on e500v1/e500v2/e500mc CPUs
Some boot loaders may not enable L1 instruction/data cache. Check if
data and instruction caches are enabled, and enable them if needed.
Signed-off-by: Nate Case <ncase@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r-- | arch/powerpc/include/asm/reg_booke.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 601ddbc46002..6bcf364cbb2f 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h | |||
@@ -389,12 +389,14 @@ | |||
389 | #define ICCR_CACHE 1 /* Cacheable */ | 389 | #define ICCR_CACHE 1 /* Cacheable */ |
390 | 390 | ||
391 | /* Bit definitions for L1CSR0. */ | 391 | /* Bit definitions for L1CSR0. */ |
392 | #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ | ||
392 | #define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ | 393 | #define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ |
393 | #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ | 394 | #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ |
394 | #define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ | 395 | #define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ |
395 | #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ | 396 | #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ |
396 | 397 | ||
397 | /* Bit definitions for L1CSR1. */ | 398 | /* Bit definitions for L1CSR1. */ |
399 | #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ | ||
398 | #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ | 400 | #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ |
399 | #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ | 401 | #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ |
400 | #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ | 402 | #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ |