diff options
author | Kumar Gala <galak@kernel.crashing.org> | 2008-08-01 12:44:11 -0400 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2008-08-03 23:18:17 -0400 |
commit | 9c4cb82515130c62224e23fdf7c13c8f6c59c614 (patch) | |
tree | f916fd843972502d918a1a03bdb99c9c2bbaa91c /arch/powerpc/include | |
parent | c7c8eede2739289df02a1ab297cc476c6f38dca7 (diff) |
powerpc: Remove use of CONFIG_PPC_MERGE
Now that arch/ppc is gone and CONFIG_PPC_MERGE is always set, remove
the dead code associated with !CONFIG_PPC_MERGE from arch/powerpc
and include/asm-powerpc.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r-- | arch/powerpc/include/asm/dcr.h | 6 | ||||
-rw-r--r-- | arch/powerpc/include/asm/i8259.h | 5 | ||||
-rw-r--r-- | arch/powerpc/include/asm/ipic.h | 7 | ||||
-rw-r--r-- | arch/powerpc/include/asm/irq.h | 288 |
4 files changed, 1 insertions, 305 deletions
diff --git a/arch/powerpc/include/asm/dcr.h b/arch/powerpc/include/asm/dcr.h index 53b283050ab3..d13fb68bb5c0 100644 --- a/arch/powerpc/include/asm/dcr.h +++ b/arch/powerpc/include/asm/dcr.h | |||
@@ -65,17 +65,13 @@ typedef dcr_host_mmio_t dcr_host_t; | |||
65 | #endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */ | 65 | #endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */ |
66 | 66 | ||
67 | /* | 67 | /* |
68 | * On CONFIG_PPC_MERGE, we have additional helpers to read the DCR | 68 | * additional helpers to read the DCR * base from the device-tree |
69 | * base from the device-tree | ||
70 | */ | 69 | */ |
71 | #ifdef CONFIG_PPC_MERGE | ||
72 | struct device_node; | 70 | struct device_node; |
73 | extern unsigned int dcr_resource_start(struct device_node *np, | 71 | extern unsigned int dcr_resource_start(struct device_node *np, |
74 | unsigned int index); | 72 | unsigned int index); |
75 | extern unsigned int dcr_resource_len(struct device_node *np, | 73 | extern unsigned int dcr_resource_len(struct device_node *np, |
76 | unsigned int index); | 74 | unsigned int index); |
77 | #endif /* CONFIG_PPC_MERGE */ | ||
78 | |||
79 | #endif /* CONFIG_PPC_DCR */ | 75 | #endif /* CONFIG_PPC_DCR */ |
80 | #endif /* __ASSEMBLY__ */ | 76 | #endif /* __ASSEMBLY__ */ |
81 | #endif /* __KERNEL__ */ | 77 | #endif /* __KERNEL__ */ |
diff --git a/arch/powerpc/include/asm/i8259.h b/arch/powerpc/include/asm/i8259.h index db1362f8c603..105ade297aad 100644 --- a/arch/powerpc/include/asm/i8259.h +++ b/arch/powerpc/include/asm/i8259.h | |||
@@ -4,14 +4,9 @@ | |||
4 | 4 | ||
5 | #include <linux/irq.h> | 5 | #include <linux/irq.h> |
6 | 6 | ||
7 | #ifdef CONFIG_PPC_MERGE | ||
8 | extern void i8259_init(struct device_node *node, unsigned long intack_addr); | 7 | extern void i8259_init(struct device_node *node, unsigned long intack_addr); |
9 | extern unsigned int i8259_irq(void); | 8 | extern unsigned int i8259_irq(void); |
10 | extern struct irq_host *i8259_get_host(void); | 9 | extern struct irq_host *i8259_get_host(void); |
11 | #else | ||
12 | extern void i8259_init(unsigned long intack_addr, int offset); | ||
13 | extern int i8259_irq(void); | ||
14 | #endif | ||
15 | 10 | ||
16 | #endif /* __KERNEL__ */ | 11 | #endif /* __KERNEL__ */ |
17 | #endif /* _ASM_POWERPC_I8259_H */ | 12 | #endif /* _ASM_POWERPC_I8259_H */ |
diff --git a/arch/powerpc/include/asm/ipic.h b/arch/powerpc/include/asm/ipic.h index 4cf35531c0ef..fb59829983b8 100644 --- a/arch/powerpc/include/asm/ipic.h +++ b/arch/powerpc/include/asm/ipic.h | |||
@@ -77,15 +77,8 @@ extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq); | |||
77 | extern u32 ipic_get_mcp_status(void); | 77 | extern u32 ipic_get_mcp_status(void); |
78 | extern void ipic_clear_mcp_status(u32 mask); | 78 | extern void ipic_clear_mcp_status(u32 mask); |
79 | 79 | ||
80 | #ifdef CONFIG_PPC_MERGE | ||
81 | extern struct ipic * ipic_init(struct device_node *node, unsigned int flags); | 80 | extern struct ipic * ipic_init(struct device_node *node, unsigned int flags); |
82 | extern unsigned int ipic_get_irq(void); | 81 | extern unsigned int ipic_get_irq(void); |
83 | #else | ||
84 | extern void ipic_init(phys_addr_t phys_addr, unsigned int flags, | ||
85 | unsigned int irq_offset, | ||
86 | unsigned char *senses, unsigned int senses_count); | ||
87 | extern int ipic_get_irq(void); | ||
88 | #endif | ||
89 | 82 | ||
90 | #endif /* __ASM_IPIC_H__ */ | 83 | #endif /* __ASM_IPIC_H__ */ |
91 | #endif /* __KERNEL__ */ | 84 | #endif /* __KERNEL__ */ |
diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h index 1ef8e304e0ea..a372f76836c2 100644 --- a/arch/powerpc/include/asm/irq.h +++ b/arch/powerpc/include/asm/irq.h | |||
@@ -25,8 +25,6 @@ | |||
25 | 25 | ||
26 | extern atomic_t ppc_n_lost_interrupts; | 26 | extern atomic_t ppc_n_lost_interrupts; |
27 | 27 | ||
28 | #ifdef CONFIG_PPC_MERGE | ||
29 | |||
30 | /* This number is used when no interrupt has been assigned */ | 28 | /* This number is used when no interrupt has been assigned */ |
31 | #define NO_IRQ (0) | 29 | #define NO_IRQ (0) |
32 | 30 | ||
@@ -326,292 +324,6 @@ static __inline__ int irq_canonicalize(int irq) | |||
326 | return irq; | 324 | return irq; |
327 | } | 325 | } |
328 | 326 | ||
329 | |||
330 | #else /* CONFIG_PPC_MERGE */ | ||
331 | |||
332 | /* This number is used when no interrupt has been assigned */ | ||
333 | #define NO_IRQ (-1) | ||
334 | #define NO_IRQ_IGNORE (-2) | ||
335 | |||
336 | |||
337 | /* | ||
338 | * These constants are used for passing information about interrupt | ||
339 | * signal polarity and level/edge sensing to the low-level PIC chip | ||
340 | * drivers. | ||
341 | */ | ||
342 | #define IRQ_SENSE_MASK 0x1 | ||
343 | #define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */ | ||
344 | #define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */ | ||
345 | |||
346 | #define IRQ_POLARITY_MASK 0x2 | ||
347 | #define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */ | ||
348 | #define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */ | ||
349 | |||
350 | |||
351 | #if defined(CONFIG_40x) | ||
352 | #include <asm/ibm4xx.h> | ||
353 | |||
354 | #ifndef NR_BOARD_IRQS | ||
355 | #define NR_BOARD_IRQS 0 | ||
356 | #endif | ||
357 | |||
358 | #ifndef UIC_WIDTH /* Number of interrupts per device */ | ||
359 | #define UIC_WIDTH 32 | ||
360 | #endif | ||
361 | |||
362 | #ifndef NR_UICS /* number of UIC devices */ | ||
363 | #define NR_UICS 1 | ||
364 | #endif | ||
365 | |||
366 | #if defined (CONFIG_403) | ||
367 | /* | ||
368 | * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has | ||
369 | * 32 possible interrupts, a majority of which are not implemented on | ||
370 | * all cores. There are six configurable, external interrupt pins and | ||
371 | * there are eight internal interrupts for the on-chip serial port | ||
372 | * (SPU), DMA controller, and JTAG controller. | ||
373 | * | ||
374 | */ | ||
375 | |||
376 | #define NR_AIC_IRQS 32 | ||
377 | #define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS) | ||
378 | |||
379 | #elif !defined (CONFIG_403) | ||
380 | |||
381 | /* | ||
382 | * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32 | ||
383 | * possible interrupts as well. There are seven, configurable external | ||
384 | * interrupt pins and there are 17 internal interrupts for the on-chip | ||
385 | * serial port, DMA controller, on-chip Ethernet controller, PCI, etc. | ||
386 | * | ||
387 | */ | ||
388 | |||
389 | |||
390 | #define NR_UIC_IRQS UIC_WIDTH | ||
391 | #define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS) | ||
392 | #endif | ||
393 | |||
394 | #elif defined(CONFIG_44x) | ||
395 | #include <asm/ibm44x.h> | ||
396 | |||
397 | #define NR_UIC_IRQS 32 | ||
398 | #define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS) | ||
399 | |||
400 | #elif defined(CONFIG_8xx) | ||
401 | |||
402 | /* Now include the board configuration specific associations. | ||
403 | */ | ||
404 | #include <asm/mpc8xx.h> | ||
405 | |||
406 | /* The MPC8xx cores have 16 possible interrupts. There are eight | ||
407 | * possible level sensitive interrupts assigned and generated internally | ||
408 | * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer. | ||
409 | * There are eight external interrupts (IRQs) that can be configured | ||
410 | * as either level or edge sensitive. | ||
411 | * | ||
412 | * On some implementations, there is also the possibility of an 8259 | ||
413 | * through the PCI and PCI-ISA bridges. | ||
414 | * | ||
415 | * We are "flattening" the interrupt vectors of the cascaded CPM | ||
416 | * and 8259 interrupt controllers so that we can uniquely identify | ||
417 | * any interrupt source with a single integer. | ||
418 | */ | ||
419 | #define NR_SIU_INTS 16 | ||
420 | #define NR_CPM_INTS 32 | ||
421 | #ifndef NR_8259_INTS | ||
422 | #define NR_8259_INTS 0 | ||
423 | #endif | ||
424 | |||
425 | #define SIU_IRQ_OFFSET 0 | ||
426 | #define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS) | ||
427 | #define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS) | ||
428 | |||
429 | #define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS) | ||
430 | |||
431 | /* These values must be zero-based and map 1:1 with the SIU configuration. | ||
432 | * They are used throughout the 8xx I/O subsystem to generate | ||
433 | * interrupt masks, flags, and other control patterns. This is why the | ||
434 | * current kernel assumption of the 8259 as the base controller is such | ||
435 | * a pain in the butt. | ||
436 | */ | ||
437 | #define SIU_IRQ0 (0) /* Highest priority */ | ||
438 | #define SIU_LEVEL0 (1) | ||
439 | #define SIU_IRQ1 (2) | ||
440 | #define SIU_LEVEL1 (3) | ||
441 | #define SIU_IRQ2 (4) | ||
442 | #define SIU_LEVEL2 (5) | ||
443 | #define SIU_IRQ3 (6) | ||
444 | #define SIU_LEVEL3 (7) | ||
445 | #define SIU_IRQ4 (8) | ||
446 | #define SIU_LEVEL4 (9) | ||
447 | #define SIU_IRQ5 (10) | ||
448 | #define SIU_LEVEL5 (11) | ||
449 | #define SIU_IRQ6 (12) | ||
450 | #define SIU_LEVEL6 (13) | ||
451 | #define SIU_IRQ7 (14) | ||
452 | #define SIU_LEVEL7 (15) | ||
453 | |||
454 | #define MPC8xx_INT_FEC1 SIU_LEVEL1 | ||
455 | #define MPC8xx_INT_FEC2 SIU_LEVEL3 | ||
456 | |||
457 | #define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1) | ||
458 | #define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2) | ||
459 | #define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3) | ||
460 | #define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4) | ||
461 | #define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1) | ||
462 | #define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2) | ||
463 | |||
464 | /* The internal interrupts we can configure as we see fit. | ||
465 | * My personal preference is CPM at level 2, which puts it above the | ||
466 | * MBX PCI/ISA/IDE interrupts. | ||
467 | */ | ||
468 | #ifndef PIT_INTERRUPT | ||
469 | #define PIT_INTERRUPT SIU_LEVEL0 | ||
470 | #endif | ||
471 | #ifndef CPM_INTERRUPT | ||
472 | #define CPM_INTERRUPT SIU_LEVEL2 | ||
473 | #endif | ||
474 | #ifndef PCMCIA_INTERRUPT | ||
475 | #define PCMCIA_INTERRUPT SIU_LEVEL6 | ||
476 | #endif | ||
477 | #ifndef DEC_INTERRUPT | ||
478 | #define DEC_INTERRUPT SIU_LEVEL7 | ||
479 | #endif | ||
480 | |||
481 | /* Some internal interrupt registers use an 8-bit mask for the interrupt | ||
482 | * level instead of a number. | ||
483 | */ | ||
484 | #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) | ||
485 | |||
486 | #else /* CONFIG_40x + CONFIG_8xx */ | ||
487 | /* | ||
488 | * this is the # irq's for all ppc arch's (pmac/chrp/prep) | ||
489 | * so it is the max of them all | ||
490 | */ | ||
491 | #define NR_IRQS 256 | ||
492 | #define __DO_IRQ_CANON 1 | ||
493 | |||
494 | #ifndef CONFIG_8260 | ||
495 | |||
496 | #define NUM_8259_INTERRUPTS 16 | ||
497 | |||
498 | #else /* CONFIG_8260 */ | ||
499 | |||
500 | /* The 8260 has an internal interrupt controller with a maximum of | ||
501 | * 64 IRQs. We will use NR_IRQs from above since it is large enough. | ||
502 | * Don't be confused by the 8260 documentation where they list an | ||
503 | * "interrupt number" and "interrupt vector". We are only interested | ||
504 | * in the interrupt vector. There are "reserved" holes where the | ||
505 | * vector number increases, but the interrupt number in the table does not. | ||
506 | * (Document errata updates have fixed this...make sure you have up to | ||
507 | * date processor documentation -- Dan). | ||
508 | */ | ||
509 | |||
510 | #ifndef CPM_IRQ_OFFSET | ||
511 | #define CPM_IRQ_OFFSET 0 | ||
512 | #endif | ||
513 | |||
514 | #define NR_CPM_INTS 64 | ||
515 | |||
516 | #define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET) | ||
517 | #define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET) | ||
518 | #define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET) | ||
519 | #define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET) | ||
520 | #define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET) | ||
521 | #define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET) | ||
522 | #define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET) | ||
523 | #define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET) | ||
524 | #define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET) | ||
525 | #define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET) | ||
526 | #define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET) | ||
527 | #define SIU_INT_USB ((uint)0x0b + CPM_IRQ_OFFSET) | ||
528 | #define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET) | ||
529 | #define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET) | ||
530 | #define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET) | ||
531 | #define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET) | ||
532 | #define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET) | ||
533 | #define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET) | ||
534 | #define SIU_INT_PCI ((uint)0x12 + CPM_IRQ_OFFSET) | ||
535 | #define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET) | ||
536 | #define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET) | ||
537 | #define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET) | ||
538 | #define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET) | ||
539 | #define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET) | ||
540 | #define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET) | ||
541 | #define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET) | ||
542 | #define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET) | ||
543 | #define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET) | ||
544 | #define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET) | ||
545 | #define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET) | ||
546 | #define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET) | ||
547 | #define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET) | ||
548 | #define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET) | ||
549 | #define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET) | ||
550 | #define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET) | ||
551 | #define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET) | ||
552 | #define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET) | ||
553 | #define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET) | ||
554 | #define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET) | ||
555 | #define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET) | ||
556 | #define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET) | ||
557 | #define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET) | ||
558 | #define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET) | ||
559 | #define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET) | ||
560 | #define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET) | ||
561 | #define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET) | ||
562 | #define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET) | ||
563 | #define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET) | ||
564 | #define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET) | ||
565 | #define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET) | ||
566 | #define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET) | ||
567 | |||
568 | #endif /* CONFIG_8260 */ | ||
569 | |||
570 | #endif /* Whatever way too big #ifdef */ | ||
571 | |||
572 | #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) | ||
573 | /* pedantic: these are long because they are used with set_bit --RR */ | ||
574 | extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; | ||
575 | |||
576 | /* | ||
577 | * Because many systems have two overlapping names spaces for | ||
578 | * interrupts (ISA and XICS for example), and the ISA interrupts | ||
579 | * have historically not been easy to renumber, we allow ISA | ||
580 | * interrupts to take values 0 - 15, and shift up the remaining | ||
581 | * interrupts by 0x10. | ||
582 | */ | ||
583 | #define NUM_ISA_INTERRUPTS 0x10 | ||
584 | extern int __irq_offset_value; | ||
585 | |||
586 | static inline int irq_offset_up(int irq) | ||
587 | { | ||
588 | return(irq + __irq_offset_value); | ||
589 | } | ||
590 | |||
591 | static inline int irq_offset_down(int irq) | ||
592 | { | ||
593 | return(irq - __irq_offset_value); | ||
594 | } | ||
595 | |||
596 | static inline int irq_offset_value(void) | ||
597 | { | ||
598 | return __irq_offset_value; | ||
599 | } | ||
600 | |||
601 | #ifdef __DO_IRQ_CANON | ||
602 | extern int ppc_do_canonicalize_irqs; | ||
603 | #else | ||
604 | #define ppc_do_canonicalize_irqs 0 | ||
605 | #endif | ||
606 | |||
607 | static __inline__ int irq_canonicalize(int irq) | ||
608 | { | ||
609 | if (ppc_do_canonicalize_irqs && irq == 2) | ||
610 | irq = 9; | ||
611 | return irq; | ||
612 | } | ||
613 | #endif /* CONFIG_PPC_MERGE */ | ||
614 | |||
615 | extern int distribute_irqs; | 327 | extern int distribute_irqs; |
616 | 328 | ||
617 | struct irqaction; | 329 | struct irqaction; |