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author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-01-04 22:16:48 -0500 |
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committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2009-01-04 22:16:48 -0500 |
commit | 4aa12f7b927c3cac0e0cf3503642597527d0ece0 (patch) | |
tree | d327446284dcce52ad3ea54ffe8a7dddfcb8b86d /arch/powerpc/include | |
parent | b58602a4bac012b5f4fc12fe6b46ab237b610d5d (diff) | |
parent | 068e8c9d02ee37c44a4d65279b3ae8188fb09e18 (diff) |
Merge commit 'kumar/kumar-next' into next
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r-- | arch/powerpc/include/asm/qe.h | 37 | ||||
-rw-r--r-- | arch/powerpc/include/asm/qe_ic.h | 21 |
2 files changed, 52 insertions, 6 deletions
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h index edee15d269ea..a0a15311d0d8 100644 --- a/arch/powerpc/include/asm/qe.h +++ b/arch/powerpc/include/asm/qe.h | |||
@@ -17,6 +17,8 @@ | |||
17 | #ifdef __KERNEL__ | 17 | #ifdef __KERNEL__ |
18 | 18 | ||
19 | #include <linux/spinlock.h> | 19 | #include <linux/spinlock.h> |
20 | #include <linux/errno.h> | ||
21 | #include <linux/err.h> | ||
20 | #include <asm/cpm.h> | 22 | #include <asm/cpm.h> |
21 | #include <asm/immap_qe.h> | 23 | #include <asm/immap_qe.h> |
22 | 24 | ||
@@ -84,7 +86,11 @@ static inline bool qe_clock_is_brg(enum qe_clock clk) | |||
84 | extern spinlock_t cmxgcr_lock; | 86 | extern spinlock_t cmxgcr_lock; |
85 | 87 | ||
86 | /* Export QE common operations */ | 88 | /* Export QE common operations */ |
89 | #ifdef CONFIG_QUICC_ENGINE | ||
87 | extern void __init qe_reset(void); | 90 | extern void __init qe_reset(void); |
91 | #else | ||
92 | static inline void qe_reset(void) {} | ||
93 | #endif | ||
88 | 94 | ||
89 | /* QE PIO */ | 95 | /* QE PIO */ |
90 | #define QE_PIO_PINS 32 | 96 | #define QE_PIO_PINS 32 |
@@ -101,16 +107,43 @@ struct qe_pio_regs { | |||
101 | #endif | 107 | #endif |
102 | }; | 108 | }; |
103 | 109 | ||
104 | extern int par_io_init(struct device_node *np); | ||
105 | extern int par_io_of_config(struct device_node *np); | ||
106 | #define QE_PIO_DIR_IN 2 | 110 | #define QE_PIO_DIR_IN 2 |
107 | #define QE_PIO_DIR_OUT 1 | 111 | #define QE_PIO_DIR_OUT 1 |
108 | extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, | 112 | extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, |
109 | int dir, int open_drain, int assignment, | 113 | int dir, int open_drain, int assignment, |
110 | int has_irq); | 114 | int has_irq); |
115 | #ifdef CONFIG_QUICC_ENGINE | ||
116 | extern int par_io_init(struct device_node *np); | ||
117 | extern int par_io_of_config(struct device_node *np); | ||
111 | extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, | 118 | extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, |
112 | int assignment, int has_irq); | 119 | int assignment, int has_irq); |
113 | extern int par_io_data_set(u8 port, u8 pin, u8 val); | 120 | extern int par_io_data_set(u8 port, u8 pin, u8 val); |
121 | #else | ||
122 | static inline int par_io_init(struct device_node *np) { return -ENOSYS; } | ||
123 | static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; } | ||
124 | static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, | ||
125 | int assignment, int has_irq) { return -ENOSYS; } | ||
126 | static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } | ||
127 | #endif /* CONFIG_QUICC_ENGINE */ | ||
128 | |||
129 | /* | ||
130 | * Pin multiplexing functions. | ||
131 | */ | ||
132 | struct qe_pin; | ||
133 | #ifdef CONFIG_QE_GPIO | ||
134 | extern struct qe_pin *qe_pin_request(struct device_node *np, int index); | ||
135 | extern void qe_pin_free(struct qe_pin *qe_pin); | ||
136 | extern void qe_pin_set_gpio(struct qe_pin *qe_pin); | ||
137 | extern void qe_pin_set_dedicated(struct qe_pin *pin); | ||
138 | #else | ||
139 | static inline struct qe_pin *qe_pin_request(struct device_node *np, int index) | ||
140 | { | ||
141 | return ERR_PTR(-ENOSYS); | ||
142 | } | ||
143 | static inline void qe_pin_free(struct qe_pin *qe_pin) {} | ||
144 | static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {} | ||
145 | static inline void qe_pin_set_dedicated(struct qe_pin *pin) {} | ||
146 | #endif /* CONFIG_QE_GPIO */ | ||
114 | 147 | ||
115 | /* QE internal API */ | 148 | /* QE internal API */ |
116 | int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); | 149 | int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); |
diff --git a/arch/powerpc/include/asm/qe_ic.h b/arch/powerpc/include/asm/qe_ic.h index 56a7745ca343..cf519663a791 100644 --- a/arch/powerpc/include/asm/qe_ic.h +++ b/arch/powerpc/include/asm/qe_ic.h | |||
@@ -17,6 +17,9 @@ | |||
17 | 17 | ||
18 | #include <linux/irq.h> | 18 | #include <linux/irq.h> |
19 | 19 | ||
20 | struct device_node; | ||
21 | struct qe_ic; | ||
22 | |||
20 | #define NUM_OF_QE_IC_GROUPS 6 | 23 | #define NUM_OF_QE_IC_GROUPS 6 |
21 | 24 | ||
22 | /* Flags when we init the QE IC */ | 25 | /* Flags when we init the QE IC */ |
@@ -54,17 +57,27 @@ enum qe_ic_grp_id { | |||
54 | QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */ | 57 | QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */ |
55 | }; | 58 | }; |
56 | 59 | ||
60 | #ifdef CONFIG_QUICC_ENGINE | ||
57 | void qe_ic_init(struct device_node *node, unsigned int flags, | 61 | void qe_ic_init(struct device_node *node, unsigned int flags, |
58 | void (*low_handler)(unsigned int irq, struct irq_desc *desc), | 62 | void (*low_handler)(unsigned int irq, struct irq_desc *desc), |
59 | void (*high_handler)(unsigned int irq, struct irq_desc *desc)); | 63 | void (*high_handler)(unsigned int irq, struct irq_desc *desc)); |
64 | unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic); | ||
65 | unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic); | ||
66 | #else | ||
67 | static inline void qe_ic_init(struct device_node *node, unsigned int flags, | ||
68 | void (*low_handler)(unsigned int irq, struct irq_desc *desc), | ||
69 | void (*high_handler)(unsigned int irq, struct irq_desc *desc)) | ||
70 | {} | ||
71 | static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic) | ||
72 | { return 0; } | ||
73 | static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic) | ||
74 | { return 0; } | ||
75 | #endif /* CONFIG_QUICC_ENGINE */ | ||
76 | |||
60 | void qe_ic_set_highest_priority(unsigned int virq, int high); | 77 | void qe_ic_set_highest_priority(unsigned int virq, int high); |
61 | int qe_ic_set_priority(unsigned int virq, unsigned int priority); | 78 | int qe_ic_set_priority(unsigned int virq, unsigned int priority); |
62 | int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high); | 79 | int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high); |
63 | 80 | ||
64 | struct qe_ic; | ||
65 | unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic); | ||
66 | unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic); | ||
67 | |||
68 | static inline void qe_ic_cascade_low_ipic(unsigned int irq, | 81 | static inline void qe_ic_cascade_low_ipic(unsigned int irq, |
69 | struct irq_desc *desc) | 82 | struct irq_desc *desc) |
70 | { | 83 | { |